ESMT
DDR SDRAM
M13L32321A (2G)
512K x 32 Bit x 2 Banks
Double Data Rate SDRAM
Features
Double-data-rate architecture, two data transfers per clock cycle
Bi-directional data strobe (DQS)
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Two bank operation
CAS Latency : 2, 2.5, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
Data mask (DM) for write masking only
V
DD
= 3.3V
±
0.3V, V
DDQ
= 3.3V
±
0.3V
Auto & Self refresh
15.6us refresh interval
Ordering Information
Product ID
M13L32321A -5BG2G
M13L32321A -6BG2G
M13L32321A -7.5BG2G
Max Freq.
200MHz (DDR400)
166MHz (DDR333)
133MHz (DDR266)
144 ball FBGA
Pb-free
Package
Comments
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
1/48
ESMT
Functional Block Diagram
CLK
CLK
CKE
Address, BA
Mode Register &
Extended Mode
Register
Clock
Generator
M13L32321A (2G)
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank A
DQS
Sense Amplifier
DM
Command Decoder
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
RAS
Control Logic
CS
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
DQ
CLK, CLK
DLL
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
2/48
ESMT
BALL CONFIGURATION (TOP VIEW)
M13L32321A (2G)
(BGA144, 12mmX12mmX1.4mm Body, 0.8mm Ball Pitch)
2
B
C
D
E
F
G
H
J
K
L
M
N
DQS0
DQ4
DQ6
DQ7
DQ17
DQ19
DQS2
DQ21
DQ22
CAS
RAS
CS
3
DM0
VDDQ
DQ5
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
WE
NC
NC
4
VSSQ
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
NC
BA
5
DQ3
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
NC
A0
6
DQ2
DQ1
VSSQ
VSSQ
VSS
Thermal
7
DQ0
VDDQ
VDD
VSS
VSS
Thermal
8
DQ31
VDDQ
VDD
VSS
VSS
Thermal
9
DQ29
DQ30
VSSQ
VSSQ
VSS
Thermal
10
DQ28
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
NC
A7
11
VSSQ
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
CLK
A8/AP
12
DM3
VDDQ
DQ26
VDDQ
DQ15
DQ13
DM1
DQ11
DQ9
NC
CLK
CKE
13
DQS3
DQ27
DQ25
DQ24
DQ14
DQ12
DQS1
DQ10
DQ8
NC
NC
VREF
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
A10
A2
A1
VSS
VDD
NC
A3
VSS
VDD
A9
A4
VSS
NC
A5
A6
Pin Description
Pin Name
Function
Address inputs
- Row address A0~A10
- Column address A0~A7
A8/AP : AUTO Precharge
BA : Bank select (2 Banks)
Data-in/Data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi- directional Data Strobe.
DQS0 correspond to the data on DQ0~DQ7;
DQS1 correspond to the data on DQ8~DQ15;
DQS2 correspond to the data on DQ16~DQ23;
DQS3 correspond to the data on DQ24~DQ31.
Pin Name
Function
DM is an input mask signal for write data.
DM0 corresponds to the data on DQ0~DQ7;
DM1 corresponds to the data on DQ8~DQ15;
DM2 corresponds to the data on DQ16~DQ23;
DM3 corresponds to the data on DQ24~DQ31.
Clock input
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
Reference Voltage
A0~A10,
BA
DM0~DM3
DQ0~DQ31
RAS
CAS
WE
CLK, CLK
CKE
CS
V
DDQ
V
SSQ
V
REF
V
SS
V
DD
DQS0~DQS3
NC
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
3/48
ESMT
Absolute Maximum Rating
Parameter
Voltage on V
DD
& V
DDQ
supply relative to V
SS
Voltage on inputs relative to V
SS
Voltage on I/O pins relative to V
SS
Operating ambient temperature
Storage temperature
Power dissipation
Short circuit current
Note:
Symbol
V
DD
, V
DDQ
V
INPUT
V
IO
T
A
T
STG
P
D
I
OS
M13L32321A (2G)
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-0.5 ~ V
DDQ
+0.5
0 ~ +70
-55 ~ +150
2
50
Unit
V
V
V
°C
°C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to V
SS
= 0V °C )
Parameter
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
V–I Matching: Pullup to Pulldown Current Ratio
Input leakage current: Any input 0V
≤
V
IN
≤
V
DD
(All other pins not tested under = 0V)
Output leakage current
(DQs are disable; 0V
≤
V
OUT
≤
V
DDQ
)
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
VI (Ratio)
I
L
I
OZ
Min
3
3
0.49*V
DDQ
V
REF
- 0.04
V
REF
+ 0.6
-0.3
-0.3
0.36
0.71
-2
-5
Max
3.6
3.6
0.51*V
DDQ
V
REF
+ 0.04
V
DDQ
+ 0.3
V
REF
- 0.6
V
DDQ
+ 0.3
V
DDQ
+ 0.6
1.4
2
5
Unit
V
V
V
V
V
V
V
V
-
3
4
1
2
Note
μ
A
μ
A
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
4/48
ESMT
DC Operation Conditions - continued
Parameter
Output High Current (Full strength driver)
(V
OUT
=V
DDQ
-0.373V, min V
REF
, min V
TT
)
Output Low Current (Full strength driver)
(V
OUT
= 0.373V, max V
REF
, max V
TT
)
Output High Current (Reduced strength driver – 60%)
(V
OUT
= V
DDQ
-0.763V, min V
REF
, min V
TT
)
Output Low Current (Reduced strength driver – 60%)
(V
OUT
= 0.763V, max V
REF
, max V
TT
)
Output High Current (Reduced strength driver – 30%)
(V
OUT
= V
DDQ
-1.056V, min V
REF
, min V
TT
)
Output Low Current (Reduced strength driver – 30%)
(V
OUT
= 1.056V, max V
REF
, max V
TT
)
Output High Current (Reduced strength driver – 15%)
(V
OUT
= V
DDQ
-1.202V, min V
REF
, min V
TT
)
Output Low Current (Reduced strength driver – 15%)
(V
OUT
= 1.202V, max V
REF
, max V
TT
)
Symbol
I
OH
I
OL
I
OH
I
OL
I
OH
I
OL
I
OH
I
OL
Min
-15
+15
-9
+9
-4.5
+4.5
-2.25
+2.25
M13L32321A (2G)
Max
Unit
mA
mA
mA
mA
mA
mA
mA
mA
Note
5, 7
5, 7
6
6
6
6
6
6
Notes:
1. V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on V
REF
may not exceed 2% of the DC value.
2. V
TT
is not applied directly to the device. V
TT
is system supply for signal termination resistors, is expected to be set equal to
V
REF
, and must track variations in the DC level of V
REF
.
3. V
ID
is the magnitude of the difference between the input level on CLK and the input level on CLK .
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages from 0.25 V to 1.0 V. For a given output, it represents the
maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the
maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
5. V
OH
= 2.65V, V
OL
=0.35V.
6. V
OH
= 2.6V, V
OL
=0.4V.
7. The values of I
OH
(DC) is based on V
DDQ
= 3V and V
TT
= 1.54V.
The values of I
OL
(DC) is based on V
DDQ
= 3V and V
TT
= 1.46V.
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
5/48
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