X9118
Dual Supply/Low Power/1024-Tap/2-Wire Bus
Data Sheet
April 9, 2014
FN8161.5
Single Digitally-Controlled (XDCP™)
Potentiometer
The X9118 is a single digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit.
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and a four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• 1024 resistor taps – 10-bit resolution
• 2-wire serial interface for write, read and transfer
operations of the potentiometer
• Wiper resistance, 40Ω typical @ 5V
• Four non-volatile data registers for each potentiometer
• Non-volatile storage of multiple wiper positions
• Power on recall: Loads saved wiper position on power-up
• Standby current < 15µA Max
• System V
CC
: 2.7V to 5.5V operation
• Analog V+/V-: -5V to +5V
• 100kΩ end-to-end resistance
• Endurance: 100,000 data changes per bit per register
• 100 years data retention
• 14 Ld TSSOP
• Low power CMOS
• Pb-free (RoHS compliant)
Ordering Information
PART NUMBER
(Notes 1, 2)
X9118TV14IZ
X9118TV14IZ-2.7
X9118TV14Z
X9118TV14Z-2.7
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
2. For Moisture Sensitivity Level (MSL), please see product information page for
X9118.
For more information on MSL, please see tech brief
TB363.
PART
MARKING
X9118 TVZI
X9118 TVZG
X9118 TVZ
X9118 TVZF
VCC LIMITS
(V)
5 ±10%
2.7 to 5.5
5 ±10%
2.7 to 5.5
POTENTIOMETER
ORGANIZATION
(kΩ)
100
100
100
100
TEMP
RANGE
(°C)
-40 to +85
-40 to +85
0 to +70
0 to +70
PACKAGE
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
PKG.
DWG. #
M14.173
M14.173
M14.173
M14.173
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas LLC 2005, 2008, 2009, 2014. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9118
Functional Diagram
V
CC
R
H
V+
2-WIRE
BUS
INTERFACE
ADDRESS
DATA
STATUS
BUS
INTERFACE
AND
CONTROL
WRITE
READ
TRANSFER
POWER ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
(DR0-DR3)
WIPER
100kΩ
1024-TAPS
POT
CONTROL
V
SS
NC
NC
R
W
R
L
V-
Detailed Functional Diagram
V
CC
V+
POWER ON
RECALL
SCL
SDA
A1
A0
INTERFACE
AND
CONTROL
CIRCUITRY
DATA
DR2
CONTROL
R
W
WP
DR3
DR0
DR1
WIPER
COUNTER
REGISTER
(WCR)
100KΩ
1024-TAPS
R
L
R
H
V
SS
V-
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable DC reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in
filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent systems
Submit Document Feedback
2
FN8161.5
April 9, 2014
X9118
Pinout
X9118
(14 LD TSSOP)
TOP VIEW
V+
NC
A0
SCL
WP
SDA
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
R
L
R
H
R
W
NC
A1
V-
DEVICE ADDRESS (A1–A0)
The address inputs are used to set the least significant 2 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input, in
order to initiate communication with the X9118. A maximum
of 4 XDCP devices may occupy the 2-wire serial bus.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to the
Data Registers.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Pin Assignments
PIN #
1
2, 10
3
4
5
6
7
8
9
11
12
13
14
PIN NAME
V+
NC
A0
SCL
WP
SDA
V
SS
V-
A1
R
W
R
H
R
L
V
CC
FUNCTION
Analog Supply Voltage
No Connect
Device Address for 2-wire bus
Serial Clock for 2-wire bus
Hardware Write Protect
Serial Data Input/Output for 2-wire bus
System Ground
Analog Supply Voltage
Device Address for 2-wire bus
Wiper terminal of the Potentiometer
High terminal of the Potentiometer
Low terminal of the Potentiometer
System Supply Voltage
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
GROUND (V
SS
)
The V
CC
pin is the system or digital supply voltage. The V
SS
pin is the system ground.
ANALOG SUPPLY VOLTAGES (V+ AND V
-
)
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper switches
while the V- supply is used to bias switches and the internal
P+ substrate of the integrated circuit. Both of these supplies
set the voltage limits of the potentiometer.
Other Pins
NO CONNECT
No connect pins should be left open. These pins are used for
Intersil manufacturing and testing purposes.
Pin Descriptions
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bi-directional serial data input/output pin for a
2-wire slave device and is used to transfer data into and out
of the device. It receives device address, opcode, wiper
register address and data sent from a 2-wire master at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock SCL.
It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open
drain output requires the use of a pull-up resistor. The user
must account for the capacitance on the bus line and the
desired rise and fall times when selecting a pull-up resistor.
2kΩ to 2.5kΩ are typical values when using the maximum
clock frequency.
SERIAL CLOCK (SCL)
This input is used by 2-wire master to supply 2-wire serial
clock to the X9118.
Principles of Operation
The X9118 is an integrated microcircuit incorporating a
resistor array and its registers and counters and the serial
interface logic providing direct communication between the
host and the digitally controlled potentiometer. This section
provides a detailed description of the following:
• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description
Submit Document Feedback
3
FN8161.5
April 9, 2014
X9118
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
10
REGISTER 1
(DR1)
10
SERIAL
BUS
INPUT
C
O
U
N
T
E
R
D
E
C
O
D
E
R
H
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
REGISTER 2
(DR2)
REGISTER 3
(DR3)
If WCR = 000[HEX] then R
W
= R
L
If WCR = 3FF[HEX] then R
W
= R
H
R
L
R
W
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Resistor Array Description
The X9118 is comprised of a resistor array. The array
contains 1023, in effect, discrete resistive segments that are
connected in series (see Figure 1). The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch (transmission gate) connected to
the wiper (R
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the wiper counter register (WCR). The 10 bits
of the WCR (WCR[9:0]) are decoded to select, and enable,
one of 1024 switches.
The WCR may be written directly. The Data Registers and
the WCR can be read and written by the host system.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL
LOW periods. The SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions,
see Figure 3.
START CONDITION
All commands to the X9118 are preceded by the start
condition, which is a HIGH-to-LOW transition of SDA while
SCL is HIGH. The X9118 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met, see Figure 3.
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA while SCL is
HIGH, see Figure 3.
ACKNOWLEDGE
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting 8 bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9118 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte, the X9118 will
respond with a final acknowledge, see Figure 2.
Serial Interface Description
SERIAL INTERFACE – 2-WIRE
The X9118 supports a bi-directional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9118 will be
considered a slave device in all applications.
Submit Document Feedback
4
FN8161.5
April 9, 2014
X9118
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACKNOWLEDGE POLLING
The disabling of the inputs during the internal nonvolatile write
operation, can be used to take advantage of the typical 5ms
EEPROM write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command the X9118
initiates the internal write cycle. The ACK polling, Flow 1, can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the X9118 is
still busy with the write operation no ACK will be returned. If the
X9118 has completed the write operation an ACK will be
returned and the master can then proceed with the next
operation.
INSTRUCTION AND REGISTER DESCRIPTION
Device Addressing: Identification Byte (ID and A)
Following a start condition, the master must output the
address of the slave it is accessing. The most significant
4 bits of the slave address are the device type identifier. The
ID[3:0] bits is the device ID for the X9118; this is fixed as
0101[B] (refer to Table 1 on page 6).
The A[1:0] bits in the ID byte are the internal slave address.
The physical device address is defined by the state of the
A1-A0 input pins. The slave address is externally specified
by the user. The X9118 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9118 to successfully
continue the command sequence. Only the device which
slave address matches the incoming device address sent by
the master executes the instruction. The A1 to A0 inputs can
be actively driven by CMOS input signals or tied to V
CC
or
V
SS
. The R/W bit is the LSB and used to set the device for
read or write operations.
INSTRUCTION BYTE AND REGISTER SELECTION
Flow 1. ACK Polling Sequence
NONVOLATILE WRITE
COMMAND COMPLETED
ENTERACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS
ISSUE STOP
ACK
RETURNED?
YES
NO
The next byte sent to the X9118 contains the instruction and
register pointer information. The three most significant bits
are used to provide the instruction opcode (I[2:0]). The RB
and RA bits point to one of the four registers. The format is
shown in Table 2.
Table 3 provides a complete summary of the instruction set
opcodes.
FURTHER
OPERATION?
NO
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
Submit Document Feedback
5
FN8161.5
April 9, 2014
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
