F1C100,F1C100 pdf中文资料,F1C100引脚图,F1C100电路-Datasheet-电子工程世界

Datasheet> 器件分类 > F1C100

文档预览

F1C100: 产品描述ARM926-EJS 16KB I-Cache/16KB D-Cache; 文件大小498KB，共39页; 制造商ETC2

下载文档全文预览

F1C100概述

ARM926-EJS 16KB I-Cache/16KB D-Cache

文档预览

下载PDF文档

全文
预览

Allwinner

F1C100 Datasheet

F1C100 Processer

Datasheet

V1.0

2011-3-31

本 F1C100 datasheet 属于珠海全志科技有限公司之商业机密；除非珠海全志科技有限公司授权，任½机构

和个人对本 F1C100 之全部或部分内容不得有复制、复印或向第三方传播之行为；珠海全志科技有限公司保

留一切法律之权利.

Allwinner

F1C100 Datasheet

Table of Contents

REVISION HISTORY .................................................................................................................. II

DESCRIPTION ......................................................................................................................... - 5 -

FEATURE .................................................................................................................................. - 5 -

FUNCTIONAL BLOCK DIAGRAM ...................................................................................... - 7 -

PIN ASSIGNMENT .................................................................................................................. - 8 -

PIN DESCRIPTION ................................................................................................................. - 8 -

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

SDR I

NTERFACE

............................................................................................................. - 8 -

NAND F

LASH

NTERFACE

............................................................................................ - 10 -

LCD I

NTERFACE

........................................................................................................... - 10 -

USB I

NTERFACE

........................................................................................................... - 11 -

OUCH

ANEL

NTERFACE

............................................................................................ - 11 -

UDIO

ODEC

NTERFACE

............................................................................................ - 11 -

TV-O

NTERFACE

..................................................................................................... - 12 -

LOCK

.......................................................................................................................... - 12 -

ENERAL

URPOSE

IO P

................................................................................................. - 12 -

ISCELLANEOUS

IGNAL

............................................................................................. - 12 -

OWER AND

ROUND

................................................................................................... - 13 -

POWER DOMAIN.................................................................................................................. - 13 -

MODULE DESCRIPTION .................................................................................................... - 13 -

8.1

8.1.1

8.1.2

8.2

8.2.1

8.2.2

8.3

8.3.1

8.3.2

8.4

8.4.1

8.5

8.5.1

8.6

8.6.1

8.7

8.8

8.8.1

8.9

8.9.1

LOCK

ONTROL

ODULE

................................................................................................. - 13 -

CCM Overview............................................................................................................. - 13 -

CCM Diagram .............................................................................................................. - 15 -

NTERRUPT

ONTROLLER

................................................................................................... - 16 -

Interrupt Overview ....................................................................................................... - 16 -

Interrupt Diagram ......................................................................................................... - 17 -

IMER

................................................................................................................................. - 17 -

Timer Overview ............................................................................................................ - 17 -

Timer Diagram.............................................................................................................. - 18 -

ULSE

IDTH

ODULATOR

................................................................................................ - 18 -

PWM Overview ............................................................................................................ - 18 -

DMA .................................................................................................................................. - 19 -

DMA Overview ............................................................................................................ - 19 -

SDRAM I

NTERFACE

........................................................................................................... - 19 -

DRAM Controller Description ..................................................................................... - 19 -

NAND F

LASH

NTERFACE

.................................................................................................. - 20 -

SD C

ARD

NTERFACE

.......................................................................................................... - 21 -

SD Card Overview........................................................................................................ - 21 -

USB I

NTERFACE

................................................................................................................. - 21 -

USB Overview .............................................................................................................. - 21 -

本 F1C100 datasheet 属于珠海全志科技有限公司之商业机密；除非珠海全志科技有限公司授权，任½机构

和个人对本 F1C100 之全部或部分内容不得有复制、复印或向第三方传播之行为；珠海全志科技有限公司保

留一切法律之权利.

Allwinner

F1C100 Datasheet

8.10

IRE

NTERFACE

........................................................................................................ - 23 -

TWI Controller Description...................................................................................... - 23 -

TWI Controller Timing Diagram .............................................................................. - 23 -

SPI Description......................................................................................................... - 24 -

SPI Timing Diagram ................................................................................................. - 24 -

UART Overview ....................................................................................................... - 26 -

UART Timing Diagram ............................................................................................ - 27 -

IR Overview ............................................................................................................. - 27 -

IR Timing Diagram................................................................................................... - 29 -

Description ............................................................................................................... - 30 -

Feature ...................................................................................................................... - 30 -

Audio Codec Block Diagram ................................................................................... - 30 -

Description ............................................................................................................... - 31 -

Feature ...................................................................................................................... - 31 -

Description ............................................................................................................... - 31 -

Port Description ........................................................................................................ - 32 -

Port Configuration Table .......................................................................................... - 32 -

Feature ...................................................................................................................... - 34 -

Block diagram .......................................................................................................... - 35 -

Feature ...................................................................................................................... - 35 -

Video Decoder Engine Overview ............................................................................. - 35 -

8.10.1

8.10.2

8.11

8.11.1

8.11.2

8.12

8.12.1

8.12.2

8.13

8.13.1

8.13.2

8.14

8.14.1

8.14.2

8.14.3

8.15

8.15.1

8.15.2

8.16

8.17

8.16.1

8.17.1

8.17.2

8.18

8.18.1

8.18.2

8.19

8.20

8.19.1

8.20.1

SPI I

NTERFACE

................................................................................................................... - 24 -

UART I

NTERFACE

.............................................................................................................. - 26 -

IR I

NTERFACE

..................................................................................................................... - 27 -

UDIO

ODEC

.................................................................................................................... - 30 -

LRADC .............................................................................................................................. - 31 -

OUCH

ANEL

..................................................................................................................... - 31 -

GPIO I

NTERFACE

................................................................................................................ - 32 -

TV E

NCODER

...................................................................................................................... - 34 -

NIVERSAL

LCD/TV T

IMING

ONTROLLER

....................................................................... - 35 -

IDEO

ECODER

NGINE

................................................................................................... - 35 -

PACKAGE SPECIFICATIONS............................................................................................. - 38 -

本 F1C100 datasheet 属于珠海全志科技有限公司之商业机密；除非珠海全志科技有限公司授权，任½机构

和个人对本 F1C100 之全部或部分内容不得有复制、复印或向第三方传播之行为；珠海全志科技有限公司保

留一切法律之权利.

F1C100

F1C100概述

文档预览

推荐资源