The ChipFET 1206-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 80 °C/W.
Document Number: 73776
S13-0297-Rev. C, 11-Feb-13
For technical questions, contact:
pmostechsupport@vishay.com
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1
Symbol
R
thJA
R
thJF
Typical
40
15
Maximum
50
20
Unit
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Si5424DC
Vishay Siliconix
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
V
GS(th)
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-State Resistance
a
Forward Transconductance
a
Dynamic
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
I
S
I
SM
V
SD
t
rr
Q
rr
t
a
t
b
I
F
= 4.3 A, dI/dt = 100 A/µs,
T
J
= 25 °C
I
S
= 4.3 A, V
GS
= 0 V
0.8
24
11
9
15
T
C
= 25 °C
6
40
1.2
36
17
A
V
ns
nC
ns
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
R
g
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
V
DD
= 15 V, R
L
= 2.5
I
D
6 A, V
GEN
= 10 V, R
g
= 1
V
DD
= 15 V, R
L
= 2.63
I
D
5.7 A, V
GEN
= 4.5 V, R
g
= 1
f = 1 MHz
V
DS
= 15 V, V
GS
= 10 V, I
D
= 4.8 A
V
DS
= 15 V, V
GS
= 4.5 V, I
D
= 4.8 A
V
DS
= 15 V, V
GS
= 0 V, f = 1 MHz
950
230
180
21
11
3.2
4.2
2.2
17
75
22
12
10
38
26
9
26
113
33
18
15
57
40
14
ns
32
17
nC
pF
V
DS
V
DS
/T
J
V
GS(th)
/T
J
V
GS(th)
I
GSS
I
DSS
I
D(on)
R
DS(on)
g
fs
V
GS
= 0 V, I
D
= 250 µA
I
D
= 250 µA
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= 0 V, V
GS
= ± 25 V
V
DS
= 30 V, V
GS
= 0 V
V
DS
= 30 V, V
GS
= 0 V, T
J
= 55 °C
V
DS
5
V, V
GS
= 10 V
V
GS
½10
V, I
D
= 4.8 A
V
GS
½4.5
V, I
D
= 4.22 A
V
DS
= 15 V, I
D
= 4.8 A
40
0.020
0.024
17
0.024
0.030
1.1
30
19.4
- 4.6
2.3
± 100
1
10
V
mV/°C
V
ns
µA
A
S
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Notes:
a. Pulse test; pulse width
300 µs, duty cycle
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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For technical questions, contact:
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Document Number: 73776
S13-0297-Rev. C, 11-Feb-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Si5424DC
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
40
V
GS
= 4
V
V
GS
= 10 thru 5
V
4
5
I
D
- Drain Current (A)
I
D
- Drain Current (A)
30
3
20
V
GS
= 3
V
2
T
J
= 25 °C
1
T
J
= 125 °C
T
J
= - 55 °C
0.6
1.2
1.8
2.4
3.0
10
V
GS
= 2
V
0
0.0
0.6
1.2
1.8
2.4
3.0
0
0.0
V
DS
- Drain-to-Source
Voltage
(V)
V
GS
- Gate-to-Source
Voltage
(V)
Output Characteristics
0.04
1500
Transfer Characteristics
R
DS(on)
- On-Resistance (mΩ)
1200
0.03
V
GS
= 4.5
V
V
GS
= 10
V
0.02
C - Capacitance (pF)
C
iss
900
600
C
oss
300
C
rss
0.01
0
8
16
24
32
40
0
0
5
10
15
20
25
30
I
D
- Drain Current (A)
V
DS
- Drain-to-Source
Voltage
(V)
On-Resistance vs. Drain Current and Gate Voltage
10
1.8
Capacitance
R
DS(on)
- On-Resistance (Normalized)
I
D
= 6 A
V
GS
- Gate-to-Source
Voltage
(V)
8
V
DS
= 15
V
6
V
DS
= 24
V
1.6
V
GS
= 10
V,
I
D
= 4.8 A
1.4
1.2
V
GS
= 4.5
V,
I
D
= 4.2 A
4
1.0
2
0.8
0
0
6
12
18
24
0.6
- 50
- 25
0
25
50
75
100
125
150
Q
g
- Total Gate Charge (nC)
T
J
- Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 73776
S13-0297-Rev. C, 11-Feb-13
For technical questions, contact:
pmostechsupport@vishay.com
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Si5424DC
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
20
10
0.06
I
D
= 4.8 A
0.05
I
S
- Source Current (A)
T
A
= 150 °C
1
R
DS(on)
- On-Resistance (Ω)
0.04
T
A
= 125 °C
T
A
= 25 °C
0.1
0.03
0.02
T
A
= 25 °C
0.01
0.01
0.001
0.0
0.00
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
2
4
6
8
10
V
SD
- Source-to-Drain
Voltage
(V)
V
GS
- Gate-to-Source
Voltage
(V)
Source-Drain Diode Forward Voltage
2.0
1.8
40
1.6
I
D
= 250
µA
Power (W)
1.4
1.2
1.0
0.8
10
0.6
0.4
- 50
30
On-Resistance vs. Gate-to-Source Voltage
50
V
GS(th)
(V)
20
- 25
0
25
50
75
100
125
150
0
10
-3
10
-2
10
-1
1
Time (s)
10
100
600
T
J
- Temperature (°C)
Threshold Voltage
100
Single Pulse Power
Limited
by
R
DS(on)
*
1 ms
10 ms
10
I
D
- Drain Current (A)
1
100 ms
1s
10 s
0.1
BVDSS Limited
0.01
T
A
= 25 C
Single Pulse
0.001
0.1
DC
10
1
100
V
DS
- Drain-to-Source
Voltage
(V)
*
V
GS
> minimum
V
GS
at
which
R
DS(on)
is specified
Safe Operating Area, Junction-to-Ambient
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For technical questions, contact:
pmostechsupport@vishay.com
Document Number: 73776
S13-0297-Rev. C, 11-Feb-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Si5424DC
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
16
8
I
D
- Drain Current (A)
Power Dissipation (W)
12
6
8
Package Limited
4
4
2
0
0
25
50
75
100
125
150
0
0
25
50
75
100
125
150
T
C
- Case Temperature (°C)
T
C
- Case Temperature (°C)
Current Derating*
Power Derating
* The power dissipation P
D
is based on T
J(max.)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 73776
S13-0297-Rev. C, 11-Feb-13
For technical questions, contact:
pmostechsupport@vishay.com
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
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