MT9D115
MT9D115 1/5‐inch
System‐On‐a‐Chip (SOC)
CMOS Digital Image Sensor
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Table 1. KEY PERFORMANCE PARAMETERS
Parameter
Pixel Size
Optical Format
Array Format (Active)
Imaging Area
CRA
Color Filter Array
Scan Mode
Shutter
Input Clock Range
Output Pixel Clock Maximum
Output MIPI Data Rate Maximum
Max. Frame Rate
Responsivity
Signal-to-Noise Ratio
Dynamic Range
Supply Voltage
Digital
Analog
I/O
MIPI
Power Consumption
Operating Temperature Range
Package
Typical Value
1.75
mm
×
1.75
mm
1/5-inch
1600 (H)
×
1200 (V) = 1.92 Mp
2.8 mm
×
2.10 mm,
3.50 mm Diagonal (4:3 Aspect Ratio)
25°
RGB Bayer
Progressive
Electronic Rolling Shutter (ERS)
6–54 MHz
85 MHz
512 Mb/s
15 fps Full Res
30 fps 800 x 600
0.65 V/Lux−sec (550 nm)
39 dB (MAX)
63.9 dB (Pixel)
1.8 V (Nominal)
2.8 V (Nominal)
1.8 V or 2.8 V (Nominal)
1.7−1.95 V
196 mW (Note 1)
–30°C to 70°C (at Junction)
Bare Die, CSP
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
•
Automatic Functions: Exposure, White
•
•
•
•
•
•
•
•
•
1. Power consumption for typical voltages at 800
×
600 video mode.
Features
•
•
•
•
2 Mp Resolution (1600 (H)
×
1200 (V))
1/5-inch Optical Format
Same or Better Image Quality Compared to MT9D112
Individual Module ID Support Through One-time Programmable
(OTP) Memory
•
Surface Fit Lens Correction (LC) to Compensate for Lens/Small
Pixel Vignetting and Corner Color Variations
Balance, Black Level Offset Correction,
Flicker Detection and Avoidance, Color
Saturation Control, Defect Identification and
Correction, Aperture Correction, and GPIO
Programmable Controls: Exposure, White
Balance, Horizontal and Vertical Blanking,
Color, Sharpness, Gamma, Lens Shading
Correction, Horizontal and Vertical Image
Flip, Zoom, Windowing, Sampling Rates,
and GPIO
15 Frames per Second (fps) at
1600(H)
×
1200 (V) with Moderate Pixel
Clock Frequency (≤ 64 MHz) to Minimize
Baseband Reception Interference and 30 fps
at 800 (H)
×
600 (V)
2
×
2 Pixel Binning to Improve Low-light
Image Quality
Support for External LED or Xenon Flash
On-chip Phase-locked Loop (PLL) to
Minimize the Number of System Clocks
Low Power Modes to Prolong Battery Life
of Portable Devices
Fail-safe I/Os with Programmable Output
Slew Rate
Industry Standard Two-wire Serial Interface
for Controls
10-bit Parallel or MIPI Serial Interfaces for
Image Data
Applications
•
Cellular Phones
•
PC Cameras
•
PDAs
©
Semiconductor Components Industries, LLC, 2010
1
January, 2017
−
Rev. 5
Publication Order Number:
MT9D115/D
MT9D115
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
MT9D115D00STCK25AC1−200
MT9D115EB3STC−CR
MT9D115W00STCK25AC1−750
Product Description
2 MP 1/5″ SOC
2 MP 1/5″ CIS SOC
2 MP 1/5″ SOC
Orderable Product Attribute Description
Die Sales, 200
mm
Thickness
Chip Tray without Protective Film
Wafer Sales, 750
mm
Thickness
FUNCTIONAL DESCRIPTION
The ON Semiconductor MT9D115 is a 1/5-inch 2 Mp
CMOS digital image sensor with an integrated advanced
camera system. This camera system features
a microcontroller (MCU), a sophisticated image flow
processor (IFP), MIPI and parallel output ports (only one
output port can be used at a time). The microcontroller
manages all functions of the camera system and sets key
operation parameters for the sensor core to optimize the
quality of raw image data entering the IFP. The IFP will be
responsible for processing and enhancing the image.
The entire system-on-a-chip (SOC) has superior low-light
performance that is particularly suitable for PC camera
ARCHITECTURE OVERVIEW
The MT9D115 combines a 2 Mp sensor core with an IFP
to form a stand-alone solution for both image acquisition
and processing. Both the sensor core and the IFP have
internal registers that can be controlled by the user. In
normal operation, an integrated microcontroller
Sensor Core
applications. The MT9D115 features ON Semiconductor’s
breakthrough low-noise CMOS imaging technology that
achieves near-CCD image quality (based on signal-to-noise
ratio and low-light sensitivity) while maintaining the
inherent size, cost, and integration advantages of CMOS.
The ON Semiconductor MT9D115 can be operated in its
default mode or programmed for frame size, exposure, gain,
and other parameters. The default mode output is
a 800
×
600 image size at 30 frames per second (fps),
assuming a 24 MHz input clock. It outputs 8-bit data, using
the parallel output port.
autonomously controls most aspects of operation.
The processed image data is transmitted to the host system
either through the parallel or MIPI interface.
Figure 1 shows the major functional blocks of the
MT9D115.
Output Interface
Image Flow Processor (IFP)
Formatter
Pixel Array
Color Pipeline
Stats Engine
FIFO
MIPI
Parallel
Internal Register Bus
POR
ROM
Two-wire Serial IF
Microcontroller
SRAM
System Control
Microcontroller Unit (MCU)
Figure 1. MT9D155 Block Diagram
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2
MT9D115
TYPICAL CONNECTION
I/O
Power
MIPI
Power
TX
PLL
Power
Digital
Core
Power
Analog
Power
R
PULL-Up5
Slave
Two-wire
Serial
Interface
V
DD
_IO
S
DATA
S
CLK
S
ADDR
V
DD
IO_TX
8
V
DD
_PLL
V
DD
V
AA6
V
AA
_PIX
6
D
OUT
[7:0]
To
Parallel
Camera
Port
PIXCLK
Active LOW Reset
Standby Mode
External Clock In
(6−54 MHz)
General Purpose
I/Os (FLASH,
OE_BAR,
D
OUT
_LSB[1:0])
RESET_BAR
STANDBY
EXTCLK
D
OUT
_N
D
OUT
_P
GPIO[3:0]
3
V
PP7
CLK_N
CLK_P
LINE_VALID
FRAME_VALID
OR
4
To
Serial
Camera
Port
2
D
GND
GND_IO
GND_PLL
A
GND
V
DD
_IO
V
DD
IO_TX/V
DD
V
AA
_PIX/
V
DD
_PLL/
V
AA
0.1
mF
0.1
mF
0.1
mF
Notes:
1. This typical configuration shows only one scenario out of multiple possible variations for this sensor.
2. If a MIPI Interface is not required, the following pads must be left floating: D
OUT
_P, D
OUT
_N, CLK_P, and CLK_N.
3. The general purpose input/output (GPIO) pads can serve multiple features that can be reconfigured. The function and direction will vary
by applications.
4. Only one of the output modes (serial or parallel) can be used at any time.
5. ON Semiconductor recommends a resistor value of 1.5 kW to V
DD
_IO for the two-wire serial interface R
PULL-UP
; however, greater values
may be used for slower transmission speed.
6. V
AA
and V
AA
_PIX may be tied together. Although separate decoupling capacitors are recommended for V
AA
and V
AA
_PIX, decoupling
capacitors can be shared if one would like to reduce module size.
7. V
PP
is the one-time programmable memory (OTPM) programming voltage and should be left floating during normal operation.
8. 1.8 V supply shared by MIPI interface and V
DD
to reduce number of decoupling caps, hence, module size. V
DD
IO_TX must be connected
to a 1.8 V power supply source even though MIPI interface is not used.
9. ON Semiconductor recommends that 0.1
mF
and 1
mF
decoupling capacitors for each power supply are mounted as close as possible to
the pad and that a 10
mF
capacitor be placed nearby off-module. Actual values and results may vary depending on layout and design
considerations. Please follow ON Semiconductor’s recommended capacitor Recommendations.
10. V
DD
_PLL and V
AA
can share the same power source in which case GND_PLL must be connected to GND.
11. Internal pull-up in RESET_BAR pin and can be left floating when not connected.
Figure 2. Typical Configuration (Connection)
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MT9D115
DECOUPLING CAPACITOR RECOMMENDATIONS
It is important to provide clean, well-regulated power to
each power supply. The customer is ultimately responsible
for ensuring that clean power is provided for their own
designs because hardware design is influenced by many
factors, including layout, operating conditions, and
component selection.
The recommendations for capacitor placement and values
listed below are based on the ON Semiconductor internal
demo camera design and verified in hardware.
ON Semiconductor recommends the following, in order
of preference:
1. Mount 0.1
mF
and 1
mF
decoupling capacitors for
each power supply as close as possible to the pad
and place a 10
mF
capacitor nearby off-module.
2. If module limitations allow for only six decoupling
capacitors for a three-regulator design (V
DD
1V2
tied to external regulator), use a 0.1
mF
and 1
mF
SIGNAL DESCRIPTIONS
Table 3. SIGNAL DESCRIPTION AND DIRECTION
Name
STANDBY
EXTCLK
S
ADDR
S
CLK
RESET_BAR (Note 4)
CLK_N (Note 5)
CLK_P (Note 5)
D
OUT
_N (Note 5)
D
OUT
_P (Note 5)
D
OUT
[7:0] (Note 1)
FRAME_VALID (Note 1)
LINE_VALID (Note 1)
PIXCLK (Note 1)
S
DATA
GPIO_0/D
OUT
_LSB[0] (Note 2)
GPIO_1/D
OUT
_LSB[1] (Note 2)
GPIO_3/OE_BAR (Note 2)
GPIO_2/FLASH (Note 2)
V
AA
V
AA
_PIX
V
DD
V
DD
_IO
V
DD
_PLL
V
DD
IO_TX
Type
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Bidirectional
Bidirectional/Output
Bidirectional/Output
Bidirectional/Output
Bidirectional/Output
Supply
Supply
Supply
Supply
Supply
Supply
Hardware standby
External clock input
Two-wire interface device select address
Two-wire interface serial clock
Hardware reset
MIPI differential clock N
MIPI differential clock P
MIPI differential data N
MIPI differential data P
Parallel image data
Parallel pixel bus frame valid
Parallel pixel bus line valid
Parallel pixel bus pixel clock
Two-wire interface serial data
General-purpose I/O or LSB for Raw 10 data output during SOC Bypass
General-purpose I/O or LSB for Raw 10 data output during SOC Bypass
General-purpose I/O or output enable
General-purpose I/O or flash control
Analog core power source 2.8 V nominal
Analog core power source 2.8 V nominal
Digital core power source 1.8 V nominal
Digital IO power source 1.8 V or 2.8 V nominal
Digital PLL power source 2.8 V nominal
Digital MIPI IO power source 1.8 V nominal.
Description
capacitor for each of the three regulated supplies.
ON Semiconductor also recommends placing a
10
mF
capacitor for each supply off-module, but
close to each supply.
3. If module limitations allow for only three
decoupling capacitors, use a 1
mF
capacitor
(preferred) or a 0.1
mF
capacitor for each of the
three regulated supplies. ON Semiconductor also
recommends placing a 10
mF
capacitor for each
supply off-module but close to each supply.
4. Give priority to the V
AA
supply for additional
decoupling capacitors.
ON Semiconductor does not recommend inductive
filtering components.
Follow best practices when performing physical layout.
Refer to the AND9503/D.
1. In serial only mode, D
OUT
[7:0], PIXCLK, and GPIO[3:0] can be left floating by setting R0x0026[1] =1. If GPIO signals are required, D
OUT
[7:0]
and PIXCLK must be tied to D
GND
and OE_BAR must be tied to V
DD
_IO. GPIO_3 should be configured as an input for OE_BAR function
and set R0x001A[8] = 1.
2. GPIO can be left floating if not used and must be programmed as outputs.
3. Must be connected to V
DD
_IO, internal 100 kW typical at 2.8 V VDDIO used.
4. Can be left floating if not used.
5. Must be connected to V
DD
, even in designs where the MIPI interface is not used.
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MT9D115
ARCHITECTURE
The MT9D115 from ON Semiconductor is the
third-generation, two-megapixel camera SOC. It is
a microprocessor-based camera system that combines
a sensor core with an image flow processor (IFP) to form
a standalone solution that includes image acquisition and
processing. Both the sensor core and IFP have internal
To External Host
Always ON
1 kB
Patch
RAM
Two-wire
Serial I/F
Slave
registers that can be accessed by an external host. In normal
operation, the integrated system microprocessor
autonomously controls most aspects of operation.
The image data is transmitted to the external host system
either through a parallel bus or a serial MIPI interface (see
Figure 3).
GPIO
Sensor
Core
Memory Data Bus
1 kB
Data
RAM
DMA
Register Bus Master
Register Bus (ICB)
Input to
IFP
Interface
MCU
IFP
Peripheral Bus (SFR)
Instruction Bus
Math Coprocessor
Sleep Unit
24 kB
Code
ROM
Output
from IFP
Interface
Parallel
Serial
Figure 3. SOC Block Diagram
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