MT9P031
1/2.5-Inch 5 Mp CMOS
Digital Image Sensor
General Description
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The ON Semiconductor MT9P031 is a 1/2.5−inch CMOS
active−pixel digital image sensor with an active imaging pixel array of
2592 H x 1944 V. It incorporates sophisticated camera functions
on−chip such as windowing, column and row skip mode, and snapshot
mode. It is programmable through a simple two−wire serial interface.
The 5 Mp CMOS image sensor features ON Semiconductor’s
breakthrough low−noise CMOS imaging technology that achieves
CCD image quality (based on signal−to−noise ratio and low−light
sensitivity) while maintaining the inherent size, cost, and integration
advantages of CMOS.
Table 1. KEY PERFORMANCE PARAMETERS
Parameter
Optical Format
Active Imager Size
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Value
1/2.5-inch (4:3)
5.70 mm (H) x 4.28 mm (V)
7.13 mm Diagonal
2592 H x 1944 V
2.2 x 2.2
μm
RGB Bayer Pattern
Global Reset Release (GRR),
Snapshot Only
Electronic Rolling Shutter (ERS)
96 Mp/s at 96 MHz (2.8 V I/O)
48 Mp/s at 48 MHz (1.8 V I/O)
Programmable up to 14 fps
Programmable up to 53 fps
12-bit, On-chip
1.4 V/lux-sec (550 nm)
70.1 dB
38.1 dB
I/O
Digital
Analog
Power Consumption
Operating Temperature
Packaging
1.7−3.1 V
1.7−1.9 V (1.8 V Nominal)
2.6−3.1 V (2.8 V Nominal)
381 mW at 14 fps Full Resolution
–30°C to +70°C
48-pin iLCC, Die
ILCC48 10x10
CASE 847AA
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Applications
•
•
•
•
High Resolution Network Cameras
Wide FOV Cameras
720 P–60 fps Cameras
Dome Cameras with Electronic Pan, Tile,
and Zoom
•
Hybrid Video Cameras with High
Resolution Stills
•
Detailed Feature Extraction for Smart
Cameras
Features
Maximum Data Rate / Pixel Clock
Frame Rate
Full Resolution
HDTV (640 x 480,
with binning)
ADC Resolution
Responsivity
Pixel Dynamic Range
SNR
MAX
Supply Voltage
•
•
•
•
•
•
•
•
•
•
•
•
•
High Frame Rate
Superior Low-light Performance
Low Dark Current
Global Reset Release, which Starts the
Exposure of All Rows Simultaneously
Bulb Exposure Mode, for Arbitrary
Exposure Times
Snapshot Mode to Take Frames on Demand
Horizontal and Vertical Mirror Image
Column and row skip modes to reduce
image size without reducing field−of−view
(FOV)
Column and Row Binning Modes to
Improve Image Quality when Resizing
Simple Two-wire Serial Interface
Programmable Controls: Gain, Frame Rate,
Frame Size, Exposure
Automatic Black Level Calibration
On-chip Phase-Locked Loop (PLL)
©
Semiconductor Components Industries, LLC, 2006
January, 2017
−
Rev. 10
1
Publication Order Number:
MT9P031/D
MT9P031
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
MT9P031D00STCC18BC1−200
MT9P031D00STMC18BC1−200
MT9P031I12STC−DP
MT9P031I12STC−DR
MT9P031I12STC−DR1
MT9P031I12STC−TP
MT9P031I12STM−DP
MT9P031I12STM−DP1
MT9P031I12STM−DR
MT9P031I12STM−DR1
Product Description
5 MP 1/3” CIS
5 MP 1/3” CIS
5 MP 1/3” CIS
5 MP 1/3” CIS
5 MP 1/3” CIS
5 MP 1/3” CIS
5 MP 1/3” CIS
5 MP 1/3” CIS
5 MP 1/3” CIS
5 MP 1/3” CIS
Orderable Product Attribute Description
Die Sales, 200
m
m Thickness
Die Sales, 200
m
m Thickness
Dry Pack with Protective Film
Dry Pack without Protective Film
Dry Pack Single Tray without Protective Film
Tape & Reel with Protective Film
Dry Pack with Protective Film
Dry Pack Single Tray with Protective Film
Dry Pack without Protective Film
Dry Pack Single Tray without Protective Film
DESCRIPTION
The MT9P031 sensor can be operated in its default mode
or programmed by the user for frame size, exposure, gain
setting, and other parameters. The default mode outputs a
full resolution image at 14 frames per second (fps).
An on−chip analog−to−digital converter (ADC) provides
12 bits per pixel. FRAME_VALID (FV) and LINE_VALID
(LV) signals are output on dedicated pins, along with a pixel
clock that is synchronous with valid data.
FUNCTIONAL OVERVIEW
The MT9P031 is a progressive−scan sensor that generates
a stream of pixel data at a constant frame rate. It uses an
on−chip, phase−locked loop (PLL) to generate all internal
clocks from a single master input clock running between
TRIGGER
Pixel Array
2752H x 2004V
The MT9P031produces extraordinarily clear, sharp
digital pictures, and its ability to capture both continuous
video and single frames makes it the perfect choice for a
wide range of consumer and industrial applications,
including cell phones, digital still cameras, digital video
cameras, and PC cameras..
6 and 27 MHz. The maximum pixel rate is 96 Mp/s,
corresponding to a clock rate of 96 MHz. Figure 1 illustrates
a block diagram of the sensor.
Array Control
Serial
Interface
SCLK
S
DATA
S
ADDR
EXTCLK
RESET_BAR
STANDBY_BAR
OE
Analog Signal Chain
Data Path
PIXCLK
D
OUT
[11:0]
LV
FV
STROBE
Figure 1. Block Diagram
User interaction with the sensor is through the two−wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 5 Mp active−pixel array. The timing and control
circuitry sequences through the rows of the array, resetting
and then reading each row in turn. In the time interval
between resetting a row and reading that row, the pixels in
the row integrate incident light. The exposure is controlled
by varying the time interval between reset and readout. Once
a row has been read, the data from the columns is sequenced
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Output
MT9P031
through an analog signal chain (providing offset correction
and gain), and then through an ADC. The output from the
ADC is a 12−bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain). The pixel data are output at a rate of up to
96 Mp/s, in addition to frame and line synchronization
signals.
V
DD
_IO
2,3
V
DD2,3
V
AA2,3
V
DD
_IO
1.5kΩ
1
1.5kΩ
1
S
ADDR
RESET_BAR
STANDBY_BAR
1μF
From
controller
Master
clock
SCLK
S
DATA
TRIGGER
EXTCLK
OE
D
GND3
V
DD
_PLL
VAA_PIX
V
AA
D
OUT
[11:0]
PIXCLK
FV
LV
STROBE
1.0kΩ
V
DD
To
controller
A
GND3
RSVD
Figure 2. Typical Configuration (Connection)
Notes:
1. A resistor value of 1.5 kΩ is recommended, but may be greater for slower two-wire speed.
2. All power supplies should be adequately decoupled.
3. All D
GND
pins must be tied together, as must all A
GND
pins, all V
DD_
IO pins, and all V
DD
pins.
VAA_PIX
VAA_PIX
TEST
D
OUT
10
44
D
OUT
11
RSVD
S
DATA
FRAME_VALID
LINE_VALID
STROBE
D
GND
V
DD_
IO
V
DD
S
ADDR
STANDBY_BAR
TRIGGER
RESET_BAR
OE
NC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
5
4
3
2
1
48
48
47
46
45
D
OUT
9
43
42
41
40
39
38
37
36
35
34
33
32
31
SCLK
TEST
A
GND
D
GND
V
DD
D
OUT
8
D
OUT
7
D
OUT
6
V
DD_
IO
D
OUT
5
D
OUT
4
D
OUT
3
D
OUT
2
D
OUT
1
D
OUT
0
PIXCLK
EXTCLK
20
21
22
23
24
25
26
27
28
29
30
V
DD_
PLL
NC
NC
NC
NC
A
GND
TEST
Figure 3. 48-Pin iLCC 10 x 10 Package Pinout Diagram (Top View)
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3
TEST
D
GND
V
AA
V
AA
NC
MT9P031
Table 3. PIN DESCRIPTION
Name
RESET_BAR
Type
Input
Description
When LOW, the MT9P031 asynchronously resets. When driven HIGH,
it resumes normal operation with all configuration registers set to factory
defaults.
External input clock.
Serial clock. Pull to V
DD_
IO with a 1.5 kΩ resistor.
When HIGH, the PIXCLK, D
OUT
, FV, LV, and STROBE outputs enter a High-Z.
When driven LOW, normal operation resumes.
Standby. When LOW, the chip enters a low-power standby mode. It resumes
normal operation when the pin is driven HIGH.
Snapshot trigger. Used to trigger one frame of output in snapshot modes,
and to indicate the end of exposure in bulb exposure modes.
Serial address. When HIGH, the MT9P031 responds to device ID (BA)
H
.
When LOW, it responds to serial device ID (90)
H
.
Serial data. Pull to V
DD_
IO with a 1.5 kΩ resistor.
Pixel clock. The D
OUT
, FV, LV, and STROBE outputs should be captured on the
falling edge of this signal.
Pixel data. Pixel data is 12-bit. MSB (D
OUT11
) through LSB (D
OUT
0) of each
pixel, to be captured on the falling edge of PIXCLK.
Frame valid. Driven HIGH during active pixels and horizontal blanking of each
frame and LOW during vertical blanking.
Line valid. Driven HIGH with active pixels of each line and LOW during
blanking periods.
Snapshot strobe. Driven HIGH when all pixels are exposing in snapshot
modes.
Digital supply voltage. Nominally 1.8 V.
IO supply voltage. Nominally 1.8 or 2.8 V.
Digital ground.
Analog supply voltage. Nominally 2.8 V.
Pixel supply voltage. Nominally 2.8 V, connected externally to V
AA
.
Analog ground.
PLL supply voltage. Nominally 2.8 V, connected externally to V
AA
.
Tie to A
GND
for normal device operation (factory use only).
Tie to D
GND
for normal device operation (factory use only).
No connect.
EXTCLK
SCLK
OE
STANDBY_BAR
TRIGGER
S
ADDR
S
DATA
PIXCLK
D
OUT[11:0]
FRAME_VALID
LINE_VALID
STROBE
V
DD
V
DD
_IO
D
GND
V
AA
VAA_PIX
A
GND
V
DD_
PLL
TEST
RSVD
NC
Input
Input
Input
Input
Input
Input
I/O
Output
Output
Output
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
−
−
−
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MT9P031
PIXEL DATA FORMAT
Pixel Array Structure
The MT9P031 pixel array consists of a 2752−column by
2004−row matrix of pixels addressed by column and row.
The address (column 0, row 0) represents the upper−right
corner of the entire array, looking at the sensor, as shown in
Figure 4.
The array consists of a 2592−column by 1944−row active
region in the center representing the default output image,
surrounded by a boundary region (also active), surrounded
by a border of dark pixels (see Table 4 and Table 5). The
boundary region can be used to avoid edge effects when
doing color processing to achieve a 2592 x 1944 result
image, while the optically black column and rows can be
used to monitor the black level.
Pixels are output in a Bayer pattern format consisting of
four “colors”−GreenR, GreenB, Red, and Blue (Gr, Gb, R,
B)−representing three filter colors. When no mirror modes
are enabled, the first row output alternates between Gr and
R pixels, and the second row output alternates between B
and Gb pixels. The Gr and Gb pixels have the same color
filter, but they are treated as separate colors by the data path
and analog signal chain.
50 black rows
4
Table 4. PIXEL TYPE BY COLUMN
Column
0–9
10–15
16–2607
2608–2617
2618–2751
Pixel Type
Dark (10)
Active boundary (6)
Active image (2592)
Active boundary (10)
Dark (134)
Table 5. PIXEL TYPE BY ROW
Column
0–49
50–53
54–1997
1998–2001
2002–2003
Pixel Type
Dark (50)
Active boundary (4)
Active image (1944)
Active boundary (3)
Dark (2)
(0,0)
(16,54)
Active Image
134 black columns
10
2592 x 1944
active pixels
6
10 black columns
4
(2751, 2003)
2 black rows
Figure 4. Pixel Array Description
column readout direction
.
.
black pixels
.
First clear
pixel (10,50)
Gr
R
Gr
R
Gr
R
Gr
row
readout
direction
B
Gb
B
Gb
B
Gb
B
...
Gr
R
Gr
R
Gr
R
Gr
B
Gb
B
Gb
B
Gb
B
Gr
R
Gr
R
Gr
R
Gr
B
Gb
B
Gb
B
Gb
B
.
.
.
Figure 5. Pixel Color Pattern Detail (Top Right Corner)
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