NCP51510, NCV51510
3 Amp
V
TT
Termination
Source / Sink Regulator for
DDR, DDR-2, DDR-3, DDR-4
The NCP51510 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration. The
NCP51510 maintains a fast transient response and only requires a
minimum V
TT
load capacitance of 10
mF
for output stability. The
NCP51510 supports remote sensing and all power requirements for
DDR V
TT
bus termination. The NCP51510 can also be used in
low−power chipsets and graphics processor cores that require
dynamically adjustable output voltages. The NCP51510 is available in
the thermally−efficient DFN10 Exposed Pad package, and is rated
both Green and Pb−Free.
Features
www.onsemi.com
DFN10
CASE 485C
MARKING DIAGRAM
51510
ALYWG
G
51510 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
•
•
•
•
Generate DDR Memory Termination Voltage (V
TT
)
For DDR, DDR−2, DDR−3 and DDR−4 Source / Sink Currents
Supports Loads Up to
±3
A (Typ), Output is Over−Current Protected
Integrated MOSFETs with Thermal Shutdown Protection
Fast Load−Transient Response
P
GOOD
Output Pin to Monitor Status of V
TT
Output Regulation
SS Input Pin for Suspend Shutdown mode
V
RI
Input Reference for Flexible Voltage Tracking
V
TTS
Input for Remote Sensing (Kelvin Connection)
Built−in Soft−Start, Under Voltage Lockout
Small, Low−Profile 10−pin, 3 x 3 mm DFN Package
NCV51510MWTAG − Wettable Flank Option for Enhanced Optical
Inspection
•
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
•
This is a Pb−Free Device
Applications
PIN CONNECTIONS
V
RO
V
CC
A
GND
V
RI
P
GOOD
10 PV
CC
9 V
TT
GND
8 P
GND
7 SS
6 V
TTS
1
2
3
4
5
(Top View)
•
•
•
•
•
•
•
•
DDR Memory Termination
Desktop PC’s, Notebooks, and Workstations
Servers and Networking equipment
Telecom/Datacom, GSM Base Station
Graphics Processor Core Supplies
Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
Supplies Power for Chipset/RAM as Low as 0.5 V
Active Source/Sink Bus Termination
ORDERING INFORMATION
Device
NCP51510MNTAG
NCV51510MNTAG*
NCV51510MWTAG*
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
DFN10
(Pb−Free)
3000 / Tape &
Reel
Package
Shipping
†
©
Semiconductor Components Industries, LLC, 2015
1
April, 2015 − Rev. 2
Publication Order Number:
NCP51510/D
NCP51510, NCV51510
PIN FUNCTION DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
−
Pin Name
V
RO
V
CC
A
GND
V
RI
P
GOOD
V
TTS
SS
P
GND
V
TT
PV
CC
THERMAL
PAD
Pin Function
OUTPUT − Buffered Output of V
RI
Reference Input pin.
INPUT − Regulator Analog Power Input pin. Connect to the system supply voltage. Bypass V
CC
to A
GND
with a 1
mF
or greater ceramic capacitor.
Analog Ground
INPUT − External Reference Input for V
TT
Output (see Figure 1 for typical application)
OUTPUT − V
TT
“Power Good” pin (open drain output)
INPUT − Remote Sense Input for V
TT
. The V
TTS
pin provides accurate remote feedback sensing of the
V
TT
output.
INPUT − Suspend Shutdown Control Input. CMOS compatible. Logic HIGH = enable,
logic LOW = shutdown. Connect to VDDQ for normal operation.
Power Ground. Internally connected to Low−side MOSFET
OUTPUT − Regulated Power Output pin
INPUT − Regulator Power Input pin. Internally connected to High−side MOSFET
Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple vias
for maximum power dissipation performance.
ABSOLUTE MAXIMUM RATINGS
Rating
PV
CC
to P
GND
V
CC
to A
GND
V
RI
, V
RO
, SS, P
GOOD
to A
GND
V
TT
to P
GND
V
TTS
to A
GND
P
GND
to A
GND
Storage Temperature
Operating Junction Temperature Range
ESD Capability, Human Body Model
ESD Capability, Machine Model
V
TT
Output Continuous RMS Current
(Note 2)
(Note 2)
100 sec
1 sec
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Symbol
−
V
CC
−
−
V
TTS
P
GND
T
stg
T
J
ESD
HBM
ESD
MM
−
Value
−0.3 to 4.3
−0.3 to 4.3
−0.3 to (V
CC
+ 0.3)
−0.3 to (PV
CC
+ 0.3)
−0.3 to (PV
CC
+ 0.3)
−0.3 to +0.3
−65 to 150
−40 to 125
2000
200
±1.6
±2.5
A
°C
V
V
V
Unit
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
DISSIPATION RATINGS
Package
10−Pin DFN
T
A
=705C Power Rate
1951 mW
Derating Factor Above T
A
= 705C
24.4 mW /
°C
www.onsemi.com
2
NCP51510, NCV51510
RECOMMENED OPERATING CONDITIONS
Rating
V
TT
Output Voltage Range
PV
CC
Input Voltage Range (Power)
V
CC
Input Voltage Range (Analog)
Logic Voltage Range
Operating Ambient Temperature Range
Symbol
V
TT,
V
TTS
PV
CC
V
CC
SS, P
GOOD
T
A
Value
0.5 to 1.5
1.1 to 3.6
V
2.7 to 3.6
0 to V
CC
−40 to +125
°C
Unit
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
PV
CC
= 1.8 V; V
CC
= 3.3 V; V
RI
= V
TTS
= 1.25 V; SS = V
CC
; (circuit of Figure 1, −40°C
≤
(T
J
= T
A
)
≤
125°C; unless otherwise noted.
Typical values are at T
A
= +25°C
Parameter
OUTPUT
V
TT
Output Voltage Range
V
TT
Load Regulation
V
TT
Line−Regulation
Feedback−Voltage Error
V
TT
Current Slew Rate
V
TT
Output Power−Supply Rejec-
tion Ratio
V
TT
Output MOSFET R
DS(on)
PV
CC
> (V
TT
+ V
DROPOUT
)
−1 A
≤
I
TT
≤
+1 A
1.4 V
≤
PV
CC
≤
3.3 V, I
OUT
=
±100
mA
V
RI
to V
TTS
,
I
TT
=
±200
mA
T
A
= −40°C to 125°C
V
TT
DV
LOAD
DV
LINE
V
TTS
I
TT
di/dt
PSRR
R
DS(on)
−17
3
80
140
140
R
FB
R
DIS
12
8
250
250
kW
W
0.5
−4
1
+17
A/ms
dB
mW
1.5
+4
V
mV
Conditions
Symbol
Min
Typ
Max
Unit
C
OUT
= 100
mF,
I
TT
= 0.1 A to 2 A
10 Hz < f < 10 kHz, I
TT
= 200 mA,
C
OUT
= 100
mF
High−side (source) (I
TT
= +100 mA)
Low−side (sink) (I
TT
= −100 mA)
V
TT
Output−to−V
TTS
Input
Discharge MOSFET R
DS(on)
SUPPLY CURRENT
Quiescent PV
CC
Current
Quiescent V
CC
Current
Shutdown PV
CC
Current
Shutdown V
CC
Current
Internal Feedback Resistance
SS = 0 V
No Load
V
RI
> 0.45 V, No Load
SS = 0 V
SS = 0V, V
RI
= 0 V
SS = 0V, V
RI
> 0.45 V
I
PVCC
I
CC
I
PVCC SD
I
CC SD
0.4
0.7
0.1
50
350
10
1.3
10
100
600
mA
mA
REFERENCE
V
RI
Input Voltage Range
V
RI
Input−Bias current
V
RO
Output Voltage
V
RO
Load Regulation
SUSPEND SHUTDOWN
SS − Suspend Shutdown Logic
Input Threshold
SS − Logic Input Current
FAULT CONDITION − CURRENT LIMIT
Current−Limit Threshold
Soft−start Current−limit time
T
A
= −40°C to +125°C
I
TT LIMIT
T
SS
1.8
3
200
4.2
A
ms
SS Logic HI (V
TT
Output Enabled)
SS Logic LOW (V
TT
Suspended)
SS = V
CC
or 0 V, T
A
= +25°C
V
IH
V
IL
I
SS
−1
2.0
0.8
+1
mA
V
T
A
= +25°C
V
CC
= 3.3 V, I
RO
= 0
I
RO
=
±5
mA
V
RI
I
RI
V
RO
DV
RO
0.5
−1
V
RI
−10
−20
V
RI
1.5
+1
V
RI
+10
+20
V
mA
mV
www.onsemi.com
3
NCP51510, NCV51510
ELECTRICAL CHARACTERISTICS
PV
CC
= 1.8 V; V
CC
= 3.3 V; V
RI
= V
TTS
= 1.25 V; SS = V
CC
; (circuit of Figure 1, −40°C
≤
(T
J
= T
A
)
≤
125°C; unless otherwise noted.
Typical values are at T
A
= +25°C (continued)
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
FAULT CONDITION − UNDER−VOLTAGE LOCKOUT
V
CC
UVLO Threshold
Wake−up, rising edge
Hysteresis Voltage
PV
CC
UVLO Threshold
Wake−up, rising edge
Hysteresis Voltage
V
RI
UVLO Voltage
V
RI
, rising edge
Hysteresis Voltage
FAULT CONDITION − THERMAL SHUTDOWN
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
FAULT CONDITION − POWER GOOD
P
GOOD
Lower trip threshold
P
GOOD
Upper trip threshold
P
GOOD
Output Low Voltage
P
GOOD
start−up delay
P
GOOD
Propagation Delay
P
GOOD
Leakage Current
With respect to feedback threshold,
hysteresis = 12 mV
I
SINK
= 4 mA (P
GOOD
MOSFET = On)
Start−up rising edge, V
TTS
within
±100
mV
of the feedback threshold
V
TTS
forced 25 mV beyond P
GOOD
trip
threshold
V
TTS
= V
RI
(P
GOOD
Hi−impedance),
P
GOOD
= V
CC
+ 0.3 V, T
A
= +25°C
−
−
−
−
T
PGOOD
I
PGOOD
1
5
2
10
−200
100
−150
150
−100
200
300
3.5
35
1
ms
ms
mA
mV
Thermal Shutdown, rising edge
Hysteresis Temperature
T
SD
T
SH
165
15
°C
V
CC UVLO
−
PV
CC
UVLO
2.50
2.70
100
0.9
55
350
50
2.90
V
mV
1.1
V
mV
−
V
RI UVLO
−
450
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
4
NCP51510, NCV51510
General*
The NCP51510 is a source/sink tracking termination
regulator specifically designed for low input voltage and
low external component count systems where space is a key
application parameter. The NCP51510 integrates a
high−performance, low−dropout (LDO) linear regulator
that is capable of both sourcing and sinking current. The
LDO regulator employs a fast feedback loop so that small
ceramic capacitors can be used to support the fast load
transient response. To achieve tight regulation with
minimum effect of trace resistance, a remote sensing input
(V
TTS
) should be connected to the positive terminal of the
output capacitors as a separate trace from the high current
path of the V
TT
output.
Generation of Internal Voltage Reference
surge currents at startup, with full current available after the
200
ms
Soft−Start circuitry has timed out.
When the SS input is driven low, the V
TT
output is
discharged to P
GND
through an internal 8
W
MOSFET. The
V
RO
output remains on when the SS input is driven low. The
NCP51510 provides an open−drain P
GOOD
“Power Good”
output that goes high when the V
TTS
Sense input is within
±150
mV of the V
RI
Reference Input. The P
GOOD
output
de−asserts within 10
ms
after the V
TTS
Sense input exceeds
the size of the P
GOOD
window. During initial V
TT
startup,
P
GOOD
asserts high 2 ms after the V
TTS
Sense input enters
P
GOOD
window. Because the P
GOOD
output is open−drain,
an external pull−up resistor is required (100 kW*) between
P
GOOD
and a stable active supply voltage rail.
Thermal Shutdown with Hysteresis
The V
TT
output voltage is regulated to (and tracks with)
the voltage on the V
RI
Reference
input. When the V
RI
input
is configured for standard DDR termination applications,
the V
RI
Reference
input can be set by an external equivalent
ratio voltage divider connected to the memory supply bus
(V
DDQ
). The NCP51510 supports V
TT
voltages from 0.5 V
to 1.5 V.
Generation of Internal Voltage Reference (cont)
When the V
RO
output is configured for DDR termination
applications, it provides a separate V
TT
output reference
voltage for the memory application. The V
RO
Reference
O
utput pin is a buffered version of the V
RI
Reference Input,
and is capable of sourcing and sinking a load of
±5
mA. The
V
RO
output becomes active when the V
RI
input > 0.45 V
and the V
CC
power rail is above the UVLO threshold. The
V
RO
Reference O
utput is independent of the SS pin
(Suspend Shutdown) state.
Fault Detection and Shutdown Function
If the NCP51510 is to operate in elevated temperatures for
long durations, care should be taken to ensure that the
maximum operating junction temperature is not exceeded.
To guarantee safe operation, the NCP51510 provides
on−chip thermal shutdown protection. When the chip
junction temperature exceeds 165°C*, the part will
shutdown. When the junction temperature falls back, to
150°C*, the device resumes normal operation. If the
junction temperature exceeds the thermal shutdown
threshold, the V
TT
output is shut off, discharged by the 8
W
internal discharge MOSFET.
Output Capacitor
Output stability is guaranteed for V
TT
output capacitance
C
OUT
from 10
mF
to 220
mF.
The ESR of C
OUT
between
2 mW and 50 mW is required to maintain stability. Use the
formula below to calculate the application’s transient
response:
DI
TT(pp)
ESR
+
DV
TT(pp)
When the SS “Suspend Shutdown” input pin is driven
high, the NCP51510 regulator begins normal operation,
with the Soft Start circuit gradually increasing output
current during the first 200
ms
in order to reduce the input
Where:
DI
TT(pp)
is the maximum peak−to−peak load current delta
and
DV
TT(pp)
is the allowable peak−to−peak voltage
tolerance.
*Typical values are used with the application description text. Please refer to the Electrical Specifications Table for a more detailed list of MIN,
MAX and TYPICAL values.
www.onsemi.com
5
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
