NB3L8543S
2.5 V/3.3 V Differential 2:1
MUX to 4 LVDS Clock
Fanout Buffer Outputs with
Clock Enable and Clock
Select
Description
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MARKING
DIAGRAM
The NB3L8543S is a high performance, low skew 1−to−4 LVDS
Clock Fanout Buffer.
The NB3L8543S features a multiplexed input which can be driven
by either a differential or single−ended input to allow for the
distribution of a lower speed clock along with the high speed system
clock.
The CLK_SEL pin will select the differential CLK and CLK inputs
when LOW (or left open and pulled LOW by the internal pull−down
resistor). When CLK_SEL is HIGH, the differential PCLK and PCLK
inputs are selected.
The common clock enable pin, CLK_EN, is synchronous so that the
outputs will only be enabled/disabled when they are already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the outputs during asynchronous assertion/deassertion of the clock
enable pin. The internal flip flop is clocked on the falling edge of the
input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Features
TSSOP−20
DT SUFFIX
CASE 948E
A
L
Y
W
G
NB3L
8543
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
+
CLK_EN
D
Q
Q0
CLK
CLK
Q0
0
Q1
Q1
Q2
1
Q2
Q3
•
•
•
•
•
•
•
•
•
•
•
•
•
Four Differential LVDS Output Pairs
Two Selectable Differential Clock Inputs
CLK/CLK Can Accept LVPECL, LVDS, HCSL, SSTL and HSTL
PCLK/PCLK Can Accept LVPECL, LVDS, CML and SSTL
Maximum Output Frequency: 650 MHz
Additive Phase Jitter, RMS: 50 fs (typical)
Output Skew: 40 ps (maximum)
Part−to−part Skew: 200 ps (maximum)
Propagation Delay: 1.9 ns (maximum)
Operating Range: V
DD
= 2.5 V
±5%
or 3.3 V
±10%
−40°C
to +85°C Ambient Operating Temperature Range
TSSOP−20 Package
These are Pb−Free Devices
+
PCLK
PCLK
CLK_SEL
+
OE
+
Q3
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2014
October, 2014
−
Rev. 1
1
Publication Order Number:
NB3L8543E/D
NB3L8543S
GND
CLK_EN
CLK_SEL
CLK
CLK
PCLK
PCLK
OE
GND
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
Q0
V
DD
Q1
Q1
Q2
Q2
GND
Q3
Q3
Figure 2. Pinout Diagram (Top View)
Table 1. PIN DESCRIPTION
Number
1, 9, 13
2
3
4
5
6
7
8
10 ,18
11, 14, 16,
19
12, 15, 17,
20
Name
GND
CLK_EN
CLK_SEL
CLK
CLK
PCLK
PCLK
OE
VDD
Q[3:0]
Q[3:0]
I/O
Power
NC
NC
Input
Input
Input
Input
NC
Power
Output
Output
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pullup
Open
Default
Description
Negative (Ground) Power Supply pins must be externally connected
to power supply to guarantee proper operation.
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW). See Figure 3.
Clock Input Select (HIGH selects PCLK/PCLK, LOW selects CLK/
CLK input
True Standard Clock Input. Float open when unused.
Invert Standard Clock Inputs. Float open when unused.
True Peripheral Clock Input. Float open when unused.
Invert Peripheral Clock Inputs. Float open when unused.
Output Enable Control. When HIGH, the outputs are active and en-
abled. When LOW, the outputs are high impedance disabled.
Positive Power Supply pin must be externally connected to power
supply to guarantee proper operation.
Invert LVDS Outputs
True LVDS Outputs
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2
NB3L8543S
Table 2. FUNCTIONS
Inputs
OE
0
1
1
1
1
CLK_EN
X
0
0
1
1
CLK_SEL
X
0
1
0
1
CLK input selected
PCLK Input Selected
CLK input selected
PCLK Input Selected
Disabled
Disabled
Enabled
Enabled
Input Function
Output Function
Outputs
Qx
HI−Z
LOW
LOW
CLK
PCLK
Qx
HI−Z
HIGH
HIGH
Invert of CLK
Invert of
PCLK
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
Figure 3. CLK_EN TIMING DIAGRAM
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NB3L8543S
Table 3. ATTRIBUTES
(Note 2)
Characteristics
Internal Input Pullup Resistor
Internal Input Pulldown Resistor
ESD Protection
Human Body Model
Machine Model
Value
50 kW
50 kW
> 2 kV
> 200 V
Level 1
UL 94 V−0 @ 0.125 in
28 to 34
430
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
(Note 3)
Symbol
V
DD
V
in
C
in
I
D
T
A
T
stg
q
JA
q
JC
T
sol
Supply Voltage
Input Voltage
Input Capacitance
Output Current
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
0 lfpm
500 lfpm
(Note 4)
TSSOP−20
TSSOP−20
Continuous
Surge
Parameter
Condition 1
Condition 2
Rating
4.6
–0.5
v
V
I
v
V
DD
+ 0.5
4
10
15
−40
to
v
+85
−65
to +150
140
50
23 to 41
265
Unit
V
V
pF
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power).
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NB3L8543S
Table 5. DC CHARACTERISTICS
V
DD
= 2.5 V
±5%
or 3.3 V
±10%,
GND = 0 V, T
A
=
−40°C
to +85°C (Note 5)
Symbol
POWER SUPPLY
V
DD
I
DD
V
IH
V
IL
I
IH
I
IL
Power Supply Voltage
Power Supply Current
Input HIGH Voltage
Input LOW Voltage
Input High Current (V
DD
= V
IN
= 3.63 V)
Input LOW Current (V
DD
= 3.63 V, V
IN
= 0 V)
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 3.3 V
V
DD
= 2.5 V
CLK_EN, OE
CLK_SEL
CLK_EN, OE
CLK_SEL
−150
−5
2
1.7
V
DD
= 3.3 V
V
DD
= 2.5 V
2.97
2.375
3.3
2.5
3.63
2.625
50
V
DD
+ 0.3
0.8
0.7
5
150
V
mA
V
V
mA
mA
Characteristic
Min
Typ
Max
Unit
LVCMOS/LVTTL INPUTS (CLK_EN, CLK_SEL, OE)
DIFFERENTIAL INPUTS
(see Figures 5 and 6) (Note 8)
V
IHD
V
ILD
V
ID
V
IHCMR
I
IH
I
IL
LVDS OUTPUTS
V
OD
DV
OD
V
OS
DV
OS
I
OZ
I
OS
V
OH
V
OL
Differential Output Voltage
VOD Magnitude Change
Differential Output Voltage Offset Voltage
VOS Magnitude Change
Output High Impedance Leakage Current
Output Short Circuit Current
Output HIGH Voltage
Output LOW Voltage
0.9
−10
−5
1.34
1.06
1.6
1.125
200
300
0
1.25
5
360
40
1.375
25
+10
mV
mV
V
mV
mA
mA
V
V
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
−
V
ILD
)
Common Mode Input Voltage; (Note 9)
Input HIGH Current
Input LOW Current
CLK
PCLK
CLK
PCLK
CLK
PCLK
CLK
PCLK
V
DD
= V
IN
= 3.63 V CLK, PCLK
CLK, PCLK
V
DD
= 3.63 V, V
IN
= 0 V CLK, PCLK
CLK, PCLK
−5
−150
0.5
1.5
0
0.5
0.15
0.30
0.5
1.5
V
DD
−0.85
V
DD
V
IHD
−0.15
V
IHD
1.3
1.0
V
DD
–0.85
V
DD
150
5
V
V
V
V
mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs terminated 100
W
across Qx and Qx, see Figure 4. DC Measurements per Figure 10 reference.
6. V
th
, V
IH
, V
IL
, and V
ISE
parameters must be complied with simultaneously.
7. V
th
is applied to the complementary input when operating in single−ended mode.
8. V
IHD
, V
ILD
, V
ID
and V
CMR
parameters must be complied with simultaneously.
9. The common mode voltage is defined as V
IH
.
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