NB3L8533
2.5V/3.3V Differential 2:1
MUX to 4 LVPECL Fanout
Buffer
Description
The NB3L8533 is a low skew 1:4 LVPECL Clock fanout buffer
designed explicitly for low output skew applications.
The NB3L8533 features a multiplexed input which can be driven by
either a differential or single−ended input to allow for the distribution
of a lower speed clock along with the high speed system clock.
The CLK_SEL pin will select the differential clock inputs, CLK and
CLK, when LOW (or left open and pulled LOW by the internal
pull−down resistor). When CLK_SEL is HIGH, the Differential
PCLK and PCLK inputs are selected.
The common enable (CLK_EN) is synchronous so that the outputs
will only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore, all associated specification limits are referenced to
the negative edge of the clock input.
Features
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MARKING
DIAGRAM
TSSOP−20
DT SUFFIX
CASE 948E
NB3L
8533
ALYW
A
WL
YY
WW
G
+
CLK_EN
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
•
•
•
•
•
•
•
•
•
•
•
•
650 MHz Maximum Clock Output Frequency
CLK/CLK can Accept LVPECL, LVDS, HCSL, STTL and HSTL
PCLK/PCLK can Accept LVPECL, LVDS, CML and SSTL
Four Differential LVPECL Clock Outputs
1.5 ns Maximum Propagation Delay
Operating Range: V
CC
= 2.375 V to 3.630 V
LVCMOS Compatible Control Inputs
Selectable Differential Clock Inputs
Synchronous Clock Enable
30 ps Max. Skew Between Outputs
−40°C to +85°C Ambient Operating Temperature Range
TSSOP−20 Package
These are Pb−Free Devices
D
Q
Q0
Q0
CLK
CLK
0
Q1
Q1
Q2
+
PCLK
PCLK
1
Q2
Q3
Q3
+
CLK_SEL
Figure 1. Simplified Logic Diagram of
NB3L8533
Applications
•
Computing and Telecom
•
Routers, Servers and Switches
•
Backplanes
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
December, 2014 − Rev. 1
Publication Order Number:
NB3L8533/D
NB3L8533
V
EE
CLK_EN
CLK_SEL
CLK
CLK
PCLK
PCLK
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
Q0
V
CC
Q1
Q1
Q2
Q2
V
CC
Q3
Q3
Figure 2. Pinout Diagram
(Top View)
Table 1. FUNCTIONS
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Input Function
CLK input selected
PCLK Inputs Selected
CLK input selected
PCLK Inputs Selected
Output Function
Disabled
Disabled
Enabled
Enabled
Outputs
Qx
LOW
LOW
CLK
PCLK
Qx
HIGH
HIGH
Invert of CLK
Invert of PCLK
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
Table 2. PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
VEE
CLK_EN
CLK_SEL
CLK
CLK
PCLK
PCLK
NC
NC
VCC
Q3
Q3
VCC
Q2
Q2
Q1
Q1
VCC
Q0
Q0
Power
LVPECL Output
LVPECL Output
Power
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
Power
LVPECL Output
LVPECL Output
I/O
Power
LVCMOS/LVTTL
Input
LVCMOS/LVTTL
Input
Input
Input
Input
Input
Pull-up
Pull-down
Pull-down
Pull-up
Pull-down
Pull-up
Open
Default
Description
Negative (Ground) Power Supply pin must be externally connect-
ed to power supply to guarantee proper operation.
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW)
Clock Input Select (HIGH selects PCLK, LOW selects CLK input)
Non−inverted Differential Clock Input. Float open when unused.
Inverted Differential Clock Input. Float open when unused.
Non−inverted Differential Clock Input. Float open when unused.
Inverted Differential Clock Input. Float open when unused.
No Connect
No Connect
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Complement Differential Output
True Differential Output
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Complement Differential Output
True Differential Output
Complement Differential Output
True Differential Output
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Complement Differential Output
True Differential Output
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NB3L8533
Table 3. ATTRIBUTES
(Note 2)
Characteristics
ESD Protection
R
PU
− Pull−up Resistor
R
PD
− Pull−down Resistor
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
TSSOP−20
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
> 2 kV
> 200 V
50 kW
50 kW
Level 1
UL 94 V−0 @ 0.125 in
289
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
I
I
out
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
0 lfpm
500 lfpm
Standard Board
TSSOP−20
TSSOP−20
TSSOP−20
Condition 1
V
EE
= 0 V
V
EE
= 0 V
Continuous
Surge
V
I
≤
V
CC
Condition 2
Rating
4.6
−0.5 to V
CC
+
0.5
50
100
−40 to +85
−65 to +150
140
50
23 to 41
265
Unit
V
V
mA
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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NB3L8533
Table 5. DC CHARACTERISTICS
V
CC
= 2.375 V to 3.630 V; V
EE
= 0 V; T
A
= −40°C to +85°C (Note 3)
Symbol
POWER SUPPLY
V
CC
I
EE
Power Supply Voltage
Power Supply Current (Outputs Open)
2.375
3.630
40
V
mA
Characteristic
Min
Typ
Max
Unit
LVPECL OUTPUTS
(Note 4)
V
OH
V
OL
V
SWING
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing, Peak−to−Peak
V
CC
−1.4
V
CC
−2.0
0.6
V
CC
−0.9
V
CC
−1.7
1.0
V
V
V
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(see Figure 5) (Note 7)
V
IHD
V
ILD
V
CMR
V
ID
I
IH
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Common Mode Input Voltage; (Note 8)
Differential Input Voltage (V
IHD
−V
ILD
)
Input HIGH Current V
IN
= V
CC
= 3.630 V
Input LOW Current V
IN
= 0 V, V
CC
= 3.630 V
CLK
PCLK
CLK
PCLK
CLK/CLKb
PCLK/PCLKb
CLK/CLKb
PCLK/PCLKb
CLK, PCLK
CLKb, PCLKb
CLK, PCLK
CLKb, PCLKb
−5
−150
0.5
1.5
0
0.5
0.5
1.5
0.15
0.3
V
CC
−0.85
V
IHD
−0.15
V
IHD
−0.30
V
CC
–0.85
1.3
1.0
150
5
V
V
V
V
mA
mA
LVCMOS/LVTTL INPUTS (CLK_EN, CLK_SEL)
V
IH
V
IL
I
IH
I
IL
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current V
IN
= V
CC
= 3.630 V
Input Low Current V
IN
= 0 V, V
CC
= 3.630 V
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
−150
−5
2.0
−0.3
V
CC
+0.3
0.8
5
150
V
V
mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and Output parameters vary 1:1 with V
CC
.
4. LVPECL outputs loaded with 50
W
to V
CC
− 2 V for proper operation.
5. V
IH
, V
IL
, V
th
and V
ISE
parameters must be complied with simultaneously.
6. V
th
is applied to the complementary input when operating in single−ended mode.
7. V
IHD
, V
ILD
, V
ID
and V
CMR
parameters must be complied with simultaneously.
8. The common mode voltage is defined as V
IH
.
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NB3L8533
Table 6. AC CHARACTERISTICS,
V
CC
= 2.375 V to 3.630 V, T
A
= −40°C to +85°C (Note 9)
Symbol
f
MAX
F
N
Characteristic
Maximum Input Clock Frequency: V
OUTpp
≥
300 mV
Phase Noise, f
C
= 156.25 MHz
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
Note 10
Note 11
Offset from Carrier
−124.4
−136.1
−144.2
−153.3
−156.2
−156.2
−156.4
1.0
1.55
Min
Typ
Max
650
Unit
MHz
dBc/
Hz
t
PLH
,
t
PHL
t
∫FN
tsk(o)
tsk (pp)
V
INpp
t
r
/t
f
ODC
Propagation Delay to Differential Outputs, @ 50 MHz
(Figures 6 and 7) (V
CC
= 3.3 V)
Additive Phase Jitter, RMS; f
C
= 156.25 MHz,
Integration Range: 12 kHz − 20 MHz
Output−to−output skew; (Note 12)
Part−to−Part Skew; (Note 13)
CLK/CLK to Q/Q
PCLK/PCLK to Q/Q
ns
0.05
30
150
150
Q
n
, Q
n
250
47
1300
600
53
ps
ps
ps
mV
ps
%
Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15)
Output rise and fall times, 20% to 80%, @ 50 MHz
Output Clock Duty Cycle
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
All parameters measured at f
MAX
unless noted otherwise.
The cycle−to−cycle jitter on the input will equal the jitter on the output. The part does not add jitter
9. Measured using a V
INPPmin
source, Reference Duty Cycle = 50% duty cycle clock source. All output loading with external 50
W
to V
CC
− 2 V.
10. Measured from the differential input crossing point to the differential output crossing point.
11. Measured from V
CC
/2 input crossing point to the differential output crossing point.
12. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross
points.
13. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the
same type of inputs on each device, the outputs are measured at the differential cross points.
14. Output voltage swing is a single−ended measurement operating in differential mode.
15. Input voltage swing is a single−ended measurement operating in differential mode.
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