NB3L8504S
2.5 V / 3.3 V 1:4 Differential
Input to LVDS Fanout Buffer
/ Translator
Description
The NB3L8504S is a differential 1:4 LVDS fanout buffer/translator
with OE control for each differential output. The differential inputs
which can be driven by either a differential or single−ended input, can
accept various logic level standards such as LVPECL, LVDS, HSTL,
HCSL and SSTL. These signals are then translated to four identical
LVDS copies of the input up to 700 MHz. As such, the NB3L8504S is
ideal for Clock distribution applications that require low skew.
The NB3L8504S is offered in the TSSOP−16 package.
Features
www.onsemi.com
MARKING
DIAGRAM*
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
1
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
NB3L
8504
ALYWG
G
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Four Differential LVDS Outputs
Each Differential Output has OE Control
700 MHz Maximum Output Frequency
660 ps Max Output Rise and Fall Times, LVCMOS
Translates Differential Input to LVDS Levels
Additive Phase Jitter RMS: < 100 fs Typical
50 ps Maximum Output Skew
350 ps Maximum Part−to−part Skew
1.3 ns Maximum Propagation Delay
Operating Range: V
CC
= 2.5 V
±
5% or 3.3 V
±
10%
−40°C to +85°C Ambient Operating Temperature
16−Pin TSSOP, 4.4 mm x 5.0 mm x 0.925 mm
These are Pb−Free Devices
Telecom
Ethernet
Networking
SONET
CLK
CLK
Applications
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2016
1
April, 2016 − Rev. 2
Publication Order Number:
NB3L8504S/D
NB3L8504S
Table 1. PIN DESCRIPTIONS AND CHARACTERISTICS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
OE0
OE1
OE2
VDD
GND
CLK
CLK
OE3
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
I/O
LVTTL/LVCMOS Input
LVTTL/LVCMOS Input
LVTTL/LVCMOS Input
Power
Power
Multi−Level Input
Multi−Level Input
LVTTL/LVCMOS Input
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
Description
Output Enable pin for Q0, Q0 outputs. Defaults High when left open; internal pull−up
resistor.
Output Enable pin for Q1, Q1 outputs. Defaults High when left open; internal pull−up
resistor.
Output Enable pin for Q2, Q2 outputs. Defaults High when left open; internal pull−up
resistor.
3.3 V / 2.5 V Positive Supply Voltage.
3.3 V / 2.5 V Negative Supply Voltage.
Non−inverting differential Clock input. Defaults Low when left open; internal pull−down
resistor.
Inverting differential Clock input. Defaults to VDD/2 when left open; internal pull−up and
pull−down resistors.
Output Enable pin for Q3, Q3 outputs. Defaults High when left open; internal pull−up
resistor.
Inverting differential Clock output.
Non−inverting differential Clock output.
Inverting differential Clock output.
Non−inverting differential Clock output.
Inverting differential Clock output.
Non−inverting differential Clock output.
Inverting differential Clock output.
Non−inverting differential Clock output.
1. All VDD and GND pins must be externally connected to a power supply for proper operation.
OE0
OE1
OE2
VDD
GND
CLK
CLK
OE3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Figure 2. NB3L8504S Pinout, 16−pin TSSOP (Top View)
Table 2. OUTPUT ENABLE FUNCTION TABLE
OE[3:0]
LOW
HIGH (Default)
Outputs – Q[0:3], Q[0:3]
High Impedance
Active
www.onsemi.com
2
NB3L8504S
Table 3. ATTRIBUTES
Characteristics
ESD Protection
R
PU
− Input Pull−up Resistor
R
PD
− Input Pull−down Resistor
C
IN
− Input Capacitance
R
IN
− Input Impedance
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
TSSOP−16
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
> 2 kV
> 200 V
50 kW
50 kW
4 pF
10 kW
Level 1
UL 94 V−0 @ 0.125 in
371
Table 4. MAXIMUM RATINGS
Symbol
V
DD
V
IN
I
out
I
OSC
Continuous Current
Surge Current
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−GND (Q or Q to GND)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder (Pb−Free)
0 lfpm
500 lfpm
(Note 3)
TSSOP−16
TSSOP−16
TSSOP−16
Parameter
Condition
GND = 0 V
GND = 0 V
LVDS Outputs
Rating
4.6
−0.5 to V
DD
+0.5
10
15
Continuous
Continuous
12
24
−40 to +85
−65 to +150
138
108
33 − 36
265
Unit
V
V
mA
mA
mA
mA
_C
_C
_C/W
_C/W
_C/W
_C
Q or Q
Q to Q to GND
TSSOP−16
T
A
T
stg
θ
JA
θ
JC
T
sol
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
www.onsemi.com
3
NB3L8504S
Table 5. DC CHARACTERISTICS
V
DD
= 2.5 V
±
5% or 3.3 V
±
10%; GND = 0 V; T
A
= −40°C to 85°C
Symbol
POWER SUPPLY / CURRENT
(Note 4)
V
DD
I
DD
Power Supply Voltage
Power Supply Current for V
DD
V
DD
= 3.3 V
V
DD
= 2.5 V
2.97
2.375
3.3
2.5
41
3.63
2.625
50
V
mA
Characteristic
Min
Typ
Max
Unit
LVDS OUTPUTS
(Note 5)
V
OD
DV
OD
V
OS
DV
OS
V
OH
V
OL
Differential Output Voltage (Figure 12) (Notes 6 and 7)
V
OD
Magnitude Change (Figure 12) (Notes 6 and 7)
Offset Voltage (Figure 13) (Notes 6 and 7)
V
OS
Magnitude Change (Figure 13) (Notes 6 and 7)
Output HIGH Voltage
Output LOW Voltage
900
1425
1075
1075
1250
250
350
450
50
1375
50
1600
mV
mV
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(see Figure 5 & 6) (Note 11)
V
IHD
V
ILD
V
ID
V
IHCMR
I
IH
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD −
V
ILD
)
Input Common Mode Voltage Range (Differential Configuration)
(Note 10) (Figure 7)
Input HIGH Current, V
DD
= V
IN
= 3.63 V
Input LOW Current, V
DD
= 3.63 V, V
IN
= 0 V
CLK, CLK
CLK
CLK
−5
−150
500
−300
150
GND + 0.5
V
DD
– 850
V
IHD
– 150
1300
V
DD
– 850
150
mV
mV
mV
mV
mA
mA
LVCMOS – OE Control Inputs
V
IH
V
IL
I
IH
I
IL
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current, V
DD
= V
IN
= 3.63 V
Input LOW Current, V
DD
= 3.63 V, V
IN
= 0 V
−150
2.0
−0.3
V
DD
+ 0.3
0.8
5
V
V
mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
4. Input pins open and output pins loaded with R
L
=100
W
across differential.
5. LVDS outputs require 100
W
receiver termination resistor between diff. pair. See Figure 14.
6. VOS max +
½
VOD max. Also see Figures 12 and 13.
7. VOS min −
½
VOD max. Also see Figures 12 and 13.
8. V
IH
, V
IL,
Vth, and V
ISE
parameters must be complied with simultaneously.
9. Vth is applied to the complementary input when operating in single−ended mode.
10. V
IHCMR
max varies 1:1 with V
DD
, V
IHCMR
min varies 1:1 with GND.
11. V
IHD
, V
ILD,
V
ID
and V
IHCMR
parameters must be complied with simultaneously.
www.onsemi.com
4
NB3L8504S
Table 6. AC CHARACTERISTICS
V
DD
= 2.5 V
±
5% or 3.3 V
±
10%; GND = 0 V; T
A
= −40°C to 85°C (Note 12) (Figure 10)
Symbol
f
MAX
V
OUTPP
tpd
t
jit
(f)
t
SKEW(o−o)
T
SKEW(pp)
t
r
/ t
f
t
DC
V
INPP
Input Clock Frequency
Characteristic
V
OUTPP
≥
250 mV @ V
INPPmax
250
0.9
0.07
0.10
350
1.3
0.08
0.105
50
350
180
45
150
350
50
660
55
1300
Min
Typ
Max
700
Unit
MHz
mV
ns
ps
ps
ps
ps
%
mV
Output Voltage Amplitude (@ V
INPPmin
) f
in
≤
700 MHz
(See Figure 3)
Differential Input to Differential Output Propagation Delay at f
MAX
@ V
DD
= 3.3 V
Additive Phase Jitter RMS (Figure 4)
Integration Range:12 kHz − 20 MHz
Output−to−output Skew (Note 14) (Figure 8)
Part−to−part Skew (Note 14)
Output Rise/Fall Times @ 50 MHz, 20% − 80%
Output Clock Duty Cycle (Input Duty Cycle = 50%)
Input Voltage Swing
(Differential Configuration) (Note 13)
f
out
= 156.25 MHz
f
out
= 100 MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
12. Measured by forcing a 50% duty cycle clock source. All LVDS output loading with an external R
L
= 100
W
across Q & Q.
13. V
INPP(max)
cannot exceed V
DD
. Input voltage swing is a single−ended measurement operating in differential mode.
14. Skew is measured between outputs under identical transition at 50 MHz.
Figure 3. Output Voltage Amplitude (V
OUTPP
) vs. Input Clock Frequency (f
in
) and Temperature (@ V
DD
= 2.5 V)
www.onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
