NB3L14S
2.5 V 1:4 LVDS Fanout
Buffer
The NB3L14S is a differential 1:4 LVDS Clock fanout buffer. The
differential inputs incorporate internal 50
W
termination resistors that
are accessed through the VT pin. The NB3L14S LVDS signals will be
buffered and replicated to identical LVDS copies of the Input
operating up to 300 MHz. As such, the NB3L14S is ideal for Clock
distribution applications that require low skew.
The NB3L14S is offered in a small 3 mm x 3 mm 16−QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
http://onsemi.com
MARKING
DIAGRAM*
16
1
•
•
•
•
•
•
Maximum Input Clock Frequency; 300 MHz
Low Output−to−Output Skew; 20 ps
450 ps Typical Propagation Delay
250 ps Typical Rise and Fall Times
Single Power Supply; V
CC
= 2.5
$
5%
These are Pb−Free Devices
1
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
NB3L
14S
ALYW
G
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
V
CC
IN
W
VT 50
50
W
IN
V
CC
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
November, 2012
−
Rev. 0
1
Publication Order Number:
NB3L14S/D
NB3L14S
Q0
16
Q1
Q1
Q2
Q2
1
2
NB3L14S
3
4
5
Q3
6
Q3
7
8
Q0
15
V
CC
GND
14
13
12 IN
11 V
T
10 NC
9
IN
Exposed Pad (EP)
Table 1. TRUTH TABLE
IN*
0
1
x
IN*
1
0
x
Q
0
1
0 (Note 1)
Q
1
0
1 (Note 1)
V
CC
V
CC
1. Outputs will be at the known state in this table at initial power up.
The outputs will also be at the known state during normal operation
when inputs are left open.
*Defaults high when left open
Figure 2. NB3L14S Pinout, 16−pin QFN
(Top View)
Table 2. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
−
Name
Q1
Q1
Q2
Q2
Q3
Q3
V
CC
V
CC
IN
NC
V
T
IN
GND
V
CC
Q0
Q0
EP
I/O
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
−
−
LVDS
No Connect
Input Termination
LVDS
−
−
LVDS Output
LVDS Output
−
Description
Non−inverted IN output. Typically loaded with 100
W
receiver termination resistor across
differential pair.
Inverted IN output. Typically loaded with 100
W
receiver termination resistor across
differential pair.
Non−inverted IN output. Typically loaded with 100
W
receiver termination resistor across
differential pair.
Inverted IN output. Typically loaded with 100
W
receiver termination resistor across
differential pair.
Non−inverted IN output. Typically loaded with 100
W
receiver termination resistor across
differential pair.
Inverted IN output. Typically loaded with 100
W
receiver termination resistor across
differential pair.
Positive Supply Voltage.
Positive Supply Voltage.
Inverted Differential Input; pin will default HIGH when left open
This is not connected.
Internal 100
W
Center−tapped Termination Pin for IN and IN, leave open for LVDS.
Non−inverted Differential Input; pin will default HIGH when left open.
Negative Supply Voltage.
Positive Supply Voltage.
Non−inverted IN output. Typically loaded with 100
W
receiver termination resistor across
differential pair.
Inverted IN output. Typically loaded with 100
W
receiver termination resistor across
differential pair.
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and is required to be
electrically and thermally connected to GND on the PC board.
http://onsemi.com
2
NB3L14S
Table 3. ATTRIBUTES
Characteristics
Moisture Sensitivity (Note 2)
Flammability Rating
Oxygen Index: 28 to 34
Value
Level 1
UL 94 V−0 @ 0.125 in
200 kW
Human Body Model
Machine Model
> 4 kV
> 200 V
440
Input Pull−up Resistors to V
CC
on Inputs
ESD Protection
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
IN
I
IN
I
OSC
Parameter
Positive Power Supply
Positive Input
Input Current Through R
T
(50
W
Resistor)
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−GND (Q or Q to GND)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
1S2P (Note 3)
QFN−16
QFN−16
QFN−16
Condition 1
GND = 0 V
GND = 0 V
Static
Surge
Q or Q
Q to Q to GND
QFN−16
Continuous
Continuous
V
IN
≤
V
CC
Condition 2
Rating
4.6
4.6
35
70
12
24
−40
to +85
−65
to +150
41.6
35.2
4.0
265
Unit
V
V
mA
mA
mA
T
A
T
stg
q
JA
q
JC
T
sol
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board
−
1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
http://onsemi.com
3
NB3L14S
Table 5. DC CHARACTERISTICS
V
CC
= 2.375 V to 2.625 V, GND = 0 V, T
A
=
−40°C
to +85°C
Symbol
I
CC
V
IHD
V
ILD
V
CMR
V
ID
R
TIN
V
OD
DV
OD
V
OS
DV
OS
V
OH
V
OL
Characteristic
Power Supply Current (Note 4)
Min
Typ
45
Max
65
Unit
mA
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 4, 8, and 9) (Note 5)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration) (Note 6)
Differential Input Voltage (V
IHD
−
V
ILD
)
Internal Input Termination Resistor
1150
GND
75
150
40
50
1800
V
IHD
−
150
1725
1800
60
mV
mV
mV
mV
W
mV
mV
mV
mV
mV
mV
LVDS OUTPUTS
(Note 7)
Differential Output Voltage (Single−Ended Measurement)
Change in Magnitude of V
OD
for Complementary Output States (Note 8)
Offset Voltage (Figure 7)
Change in Magnitude of V
OS
for Complementary Output States (Note 8)
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 10)
900
250
0
1125
0
350
1
1250
1
1425
1075
450
25
1375
25
1600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input pins, IN = 300 mV, IN = 1 V. Output pins loaded with R
L
= 100
W
across the outputs.
5. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
6. V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
7. LVDS outputs require 100
W
receiver termination resistor between differential pair. See Figure 6.
8. Parameter guaranteed by design verification not tested in production.
9. V
OH
max = V
OS
max +
½
V
OD
max.
10. V
OL
max = V
OS
min
−
½
V
OD
max.
http://onsemi.com
4
NB3L14S
Table 6. AC CHARACTERISTICS
(V
CC
= 2.375 V to 2.625 V, GND = 0 V)
−40°C
to +85°C
Symbol
f
inMax
V
OUTPP
t
PLH
,
t
PHL
t
SKEW
V
INPP
t
r
t
f
Characteristic
Maximum Input Clock Frequency
Output Voltage Amplitude (@ V
INPPmin
)
Differential Input to Differential Output, IN to Q
Propagation Delay @ 50 MHz
Within Device Output−to−Output Skew (Note 12)
Device−to−Device Skew (Note 12)
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 11)
Output Rise/Fall Times @ 50 MHz
(20%
−
80%)
Q, Q
150
250
f
in
≤
300 MHz
Min
300
250
300
350
450
5
30
450
600
20
200
1800
350
Typ
Max
Unit
MHz
mV
ps
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input voltage swing is a single−ended measurement operating in differential mode.
12. Skew is measured between outputs under identical transition @ 50 MHz.
400
OUTPUT VOLTAGE AMPLITUDE (mV)
350
300
250
200
150
100
50
0
0
100
200
300
400
INPUT CLOCK FREQUENCY (MHz)
Figure 3. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
in
) and Temperature (@ V
CC
= 2.5 V)
http://onsemi.com
5
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
