MTP2N40E
Designer’s™ Data Sheet
TMOS E−FET.™
Power Field Effect
Transistor
N−Channel Enhancement−Mode Silicon
Gate
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced TMOS E−FET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain−to−source
diode with a fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
•
Robust High Voltage Termination
•
Avalanche Energy Specified
•
Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
•
Diode is Characterized for Use in Bridge Circuits
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
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TMOS POWER FET
2.0 AMPERES, 400 VOLTS
R
DS(on)
= 3.5
W
TO−220AB
CASE 221A−06
Style 5
D
®
G
S
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−Source Voltage
Drain−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−Source Voltage — Continuous
Gate−Source Voltage
— Non−Repetitive (t
p
≤
10 ms)
Drain Current — Continuous
Drain Current
— Continuous @ 100°C
Drain Current
— Single Pulse (t
p
≤
10
μs)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy — Starting T
J
= 25°C
(V
DD
= 100 Vdc, V
GS
= 10 Vdc, Peak I
L
= 3.0 Apk, L = 10 mH, R
G
= 25
Ω)
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
Value
400
400
±
20
±
40
2.0
1.5
6.0
40
0.32
−55
to 150
45
3.13
62.5
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
°C
mJ
°C/W
°C
I
DM
P
D
T
J
, T
stg
E
AS
R
θJC
R
θJA
T
L
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred
devices are Motorola recommended choices for future use and best overall value.
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 1
1
Publication Order Number:
MTP2N40E/D
MTP2N40E
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
μAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 400 Vdc, V
GS
= 0 Vdc)
(V
DS
= 400 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
μAdc)
Temperature Coefficient (Negative)
Static Drain−Source On−Resistance (V
GS
= 10 Vdc, I
D
= 1.0 Adc)
Drain−Source On−Voltage (V
GS
= 10 Vdc)
(I
D
= 2.0 Adc)
(I
D
= 1.0 Adc, T
J
= 125°C)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 1.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 320 Vdc, I
D
= 2.0 Adc,
V
GS
= 10 Vdc)
(V
DD
= 200 Vdc, I
D
= 2.0 Adc,
V
GS
= 10 Vdc,
R
G
= 9.1
Ω)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 2.0 Adc, V
GS
= 0 Vdc)
(I
S
= 2.0 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
V
SD
Vdc
—
—
—
—
—
—
0.88
0.76
156
99
57
0.89
1.2
—
—
—
—
—
μC
nH
—
—
—
3.5
4.5
7.5
—
—
—
nH
ns
—
—
—
—
—
—
—
—
8.0
8.4
12
11
8.6
2.6
3.2
5.0
16
14
26
20
12
—
—
—
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
—
—
—
229
34
7.3
320
40
10
pF
V
GS(th)
2.0
—
—
—
—
0.5
3.2
7.0
3.1
7.3
—
1.0
4.0
—
3.5
8.4
7.4
—
mhos
Vdc
mV/°C
Ohms
Vdc
V
(BR)DSS
400
—
—
—
—
—
451
—
—
—
—
—
10
100
100
Vdc
mV/°C
μAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
R
DS(on)
V
DS(on)
g
FS
Reverse Recovery Time
(I
S
= 2.0 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/μs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width
≤
300
μs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
t
rr
t
a
t
b
Q
RR
L
D
L
S
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MTP2N40E
TYPICAL ELECTRICAL CHARACTERISTICS
4
I D , DRAIN CURRENT (AMPS)
3.2
T
J
= 25°C
8V
7V
2.4
I D , DRAIN CURRENT (AMPS)
V
GS
= 10 V
4
V
DS
≥
10 V
3
2
1.6
6V
0.8
5V
0
0
4
8
12
16
20
1
100°C
0
25°C
T
J
= −55°C
2
3
4
5
6
7
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
8
V
GS
= 10 V
T
J
= 100°C
5
4.5
T
J
= 25°C
6
4
V
GS
= 10 V
3.5
15 V
3
2.5
4
25°C
2
−55
°C
0
0
1
2
I
D
, DRAIN CURRENT (AMPS)
3
4
0
0.5
1
1.5
2
2.5
3
3.5
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2.5
2
V
GS
= 10 V
I
D
= 1 A
1000
V
GS
= 0 V
I DSS , LEAKAGE (nA)
1.5
T
J
= 125°C
100
1
0.5
0
−50
−25
0
25
50
75
100
125
150
10
0
100
200
300
4
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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MTP2N40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate
of average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
500
400
C, CAPACITANCE (pF)
V
DS
= 0 V
V
GS
= 0 V
T
J
= 25°C
1000
V
GS
= 0 V
T
J
= 25°C
The capacitance (C
iss
) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to
the on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 8) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
inductive; the data in the figure is taken with a resistive load,
which approximates an optimally snubbed inductive load.
Power MOSFETs may be safely operated into an inductive
load; however, snubbing reduces switching losses.
C
iss
C, CAPACITANCE (pF)
C
iss
100
C
oss
10
C
rss
300
C
iss
200
C
rss
100
0
−10
C
rss
−5
V
GS
0
V
DS
5
C
oss
1
10
10
15
20
25
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1a. Capacitance Variation
Figure 1b. High Voltage Capacitance
Variation
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4
MTP2N40E
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
12
10
8
6
4
2
0
Q3
2
V
DS
4
6
Q
T
, TOTAL CHARGE (nC)
8
0
QT
300
V
GS
Q1
Q2
I
D
= 2 A
T
J
= 25°C
100
200
400
100
V
DD
= 200 V
I
D
= 2 A
V
GS
= 10 V
T
J
= 25°C
t, TIME (ns)
t
d(off)
10
t
f
t
r
t
d(on)
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
1
10
R
G
, GATE RESISTANCE (OHMS)
1
0
Figure 7. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 8. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
2
V
GS
= 0 V
T
J
= 25°C
I S , SOURCE CURRENT (AMPS)
1.5
1
0.5
0
0.5
0.6
0.7
0.8
0.9
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded and the
transition time (t
r
,t
f
) do not exceed 10
μs.
In addition the
total power averaged over a complete switching cycle must
not exceed (T
J(MAX)
−
T
C
)/(R
θJC
).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with
an increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry custom.
The energy rating must be derated for temperature as
shown in the accompanying graph (Figure 11). Maximum
energy at currents below rated continuous I
D
can safely be
assumed to equal the values indicated.
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