NCP5220A
3−in−1 PWM Dual Buck and
Linear Power Controller
The NCP5220A 3−in−1 PWM Dual Buck and Linear Power
Controller, is a complete power solution for MCH and DDR memory.
This IC combines the efficiency of PWM controllers for the VDDQ
supply and the MCH core supply voltage with the simplicity of linear
regulator for the VTT termination voltage.
This IC contains two synchronous PWM buck controllers for
driving four external N−Ch FETs to form the DDR memory supply
voltage (VDDQ) and the MCH regulator. The DDR memory
termination regulator (VTT) is designed to track at half of the
reference voltage with sourcing and sinking current.
Protective features include, soft−start circuitry, undervoltage
monitoring of 5VDUAL, BOOT voltage and thermal shutdown. The
device is housed in a thermal enhanced space−saving DFN−20
package.
Features
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20
DFN−20
MN SUFFIX
CASE 505AB
1
MARKING DIAGRAM
•
Incorporates Synchronous PWM Buck Controllers for VDDQ and
•
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VMCH
Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A
All External Power MOSFETs are N−Channel
Adjustable VDDQ and VMCH by External Dividers
VTT Tracks at Half the Reference Voltage
Fixed Switching Frequency of 250 kHz for VDDQ and VMCH
Doubled Switching Frequency of 500 kHz for VDDQ Controller in
Standby Mode to Optimize Inductor Current Ripple and Efficiency
Soft−Start Protection for All Controllers
Undervoltage Monitor of Supply Voltages
Overcurrent Protections for DDQ and VTT Regulators
VTT Regulators Soft−Start Current Protection
Fully Complies with ACPI Power Sequencing Specifications
Short Circuit Protection Prevents Damage to Power Supply Due to
Reverse DIMM Insertion
Thermal Shutdown
5x6 DFN−20 Package
Pb−Free Package is Available*
1
N5220A
AWLYYWW
G
G
N5220A = Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
COMP
FBDDQ
SS
PGND
VTT
VDDQ
AGND
FBVTT
SLP_S5
FB1P5
SW_DDQ
BG_DDQ
TG_DDQ
BOOT
5VDUAL
COMP_1P5
SLP_S3
TG_1P5
BG_1P5
GND_1P5
Typical Applications
NOTE: Pin 21 is the thermal pad
on the bottom of the device.
•
DDR I and DDR II Memory and MCH Power Supply
ORDERING INFORMATION
Device
NCP5220AMNR2
NCP5220AMNR2G
Package
DFN−20
Shipping
†
2500/Tape & Reel
DFN−20 2500/Tape & Reel
(Pb−Free)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NCP5220A/D
1
December, 2005 − Rev. 4
NCP5220A
SLP_S3
SLP_S3
SLP_S5
SS
5VDUAL
CSS
VTT
1.25 V,
2.0 Apk
COUT2
FBVTT
VTT
M1
TG_DDQ
L
SLP_S5
BOOT
13 V
Zener
12 V
5VDUAL
VDDQ
2.5 V, 20 A
AGND
NCP5220A
SW_DDQ
BG_DDQ
M2
COUT1
CZM2
R5
RZM2
CZM1
COMP_1P5
RZM1
CPM1
FB1P5
5VDUAL
PGND
COMP
CZ1
CZ2
CP1
RZ1
FBDDQ
RZ2
R1
R6
M3
VMCH
L
TG_1P5
1.5 V, 10 A
COUT3
M4
BG_1P5
PGND
VDDQ
R2
Figure 1. Application Diagram
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2
NCP5220A
VREF
VOLTAGE
and CURRENT
REFERENCE
SLP_S5
SLP_S3
VCC
R10
VREF
R11
VOCP
+
+
−
VCC
TG_DDQ
M1
L
PGND
VCC
BG_DDQ
PGND
COMP
VREF
AMP
A1
FBDDQ
VCC
M3
TP_1P5
1805 Phase
Shift
PGND
VCC
BG_1P5
M4
COUT3
L2
VMCH
CZ1
CP1
RZ1
RZ2
5VDUAL
R2
CZ2
R1
M2
COUT1
SW_DDQ
VDDQ
5VDUAL
BOOT_
UVLO
_BOOTGD
CONTROL
LOGIC
V
CC
_VREFGD
TSD
S0
S3
THERMAL
SHUTDOWN
12 V
BOOT
13 V
ZENER
5VDUAL
5VDUAL
5VDUAL
R12
VREF
R13
_5VDLGD
5VDUAL_
UVLO
VDDQ
and
V1P5
PWM
LOGIC
ILIM
SS
CSS
OSC
S0
S3
PGND
PGND
GND_1P5
COMP_1P5
VREF
AMP_MCH
A1
CZM1
CPM1
RZM1
FB1P5
CZM2
RZM2
RM1
RM2
5VDUAL
S0
R16
M2
R17
VTT
Regulation
Control
R18
VDDQ
AGND
VTT
5VDUAL
VTT
COUT2
M3
R19
AGND
AGND
PGND
FBVTT
Figure 2. Internal Block Diagram
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3
NCP5220A
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Symbol
COMP
FBDDQ
SS
PGND
VTT
VDDQ
AGND
FBVTT
SLP_S5
FB1P5
GND_1P5
BG_1P5
TG_1P5
SLP_S3
COMP_1P5
5VDUAL
BOOT
TG_DDQ
BG_DDQ
SW_DDQ
TH_PAD
VDDQ error amplifier compensation node.
DDQ regulator feedback pin.
Soft−start pin of DDQ and MCH.
Power ground.
VTT regulator output.
Power input for VTT linear regulator.
Analog ground connection and remote ground sense.
VTT regulator pin for closed loop regulation.
Active LOW control signal to activate S5 Power OFF State.
V1P5 switching regulator feedback pin.
Power ground for V1P5 regulator.
Gate driver output for V1P5 regulator low side N−Channel Power FET.
Gate driver output for V1P5 regulator high side N−Channel Power FET.
Active LOW control signal to activate S3 sleep state.
V1P5 error amplifier compensation node.
5.0 V dual supply input, which is monitored by undervoltage lock out circuitry.
Gate driver input supply, which is monitored by undervoltage lock out circuitry, and a boost capacitor connection
between SWDDQ and this pin.
Gate driver output for DDQ regulator high side N−Channel Power FET.
Gate driver output for DDQ regulator low side N−Channel Power FET.
DDQ regulator switch node and current limit sense input.
Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under the IC.
Description
MAXIMUM RATINGS
Rating
Power Supply Voltage (Pin 16) to AGND (Pin 7)
BOOT (Pin 17) to AGND (Pin 7)
Gate Drive (Pins 12, 13, 18, 19) to AGND (Pin 7)
Input / Output Pins to AGND (Pin 7)
Pins 1−3, 5, 6, 8−10, 14−15, 20
PGND (Pin 4), GND_1P5 (Pin 11) to AGND (Pin 7)
Thermal Characteristics
DFN−20 Plastic Package
Thermal Resistance, Junction−to−Air
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
Moisture Sensitivity Level
Symbol
5VDUAL
BOOT
Vg
V
IO
−0.3, 6.0
V
GND
R
qJA
−0.3, 0.3
35
V
V
°C/W
Value
−0.3, 6.0
−0.3, 14
−0.3 DC,
−4.0 for
t100
ns; 14
Unit
V
V
V
T
J
T
A
T
stg
MSL
0 to +150
0 to +70
−55 to +150
2.0
°C
°C
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM)
"2.0
kV per JEDEC standard:
JESD22–A114. Machine Model (MM)
"200
V per JEDEC standard: JESD22–A115.
2. Latchup Current Maximum Rating:
"150
mA per JEDEC standard: JESD78.
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4
NCP5220A
ELECTRICAL CHARACTERISTICS
(5VDUAL = 5.0 V, BOOT = 12 V, T
A
= 0°C to 70°C, L = 1.7
mH,
COUT1 = 3770
mF,
COUT2 = 470
mF,
COUT3 = NA, CSS = 33 nF, R1 = 2.166 kW, R2 = 2.0 kW, RZ1 = 20 kW, RZ2 = 8.0
W,
CP1 = 10 nF,
CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 kW, RM2 = 2.0 kW, RZM1 = 20 kW, RZM2 = 8.0
W,
CPM1 = 10 nF, CZM1 = 6.8 nF,
CZM2 = 100 nf for min/max values unless otherwise noted). Duplicate component values of MCH regulator from DDQ.
Characteristic
SUPPLY VOLTAGE
5VDUAL Supplier Rail Voltage
BOOT Supplier Rail Voltage at S0
SUPPLY CURRENT
S0 Mode Supply Current from 5VDUAL
I5VDL_S0
SLP_S5 = HIGH, SLP_S3 = HIGH,
BOOT = 12 V, TG_1P5 and BG_1P5
Open
SLP_S5 = HIGH, SLP_S3 = LOW,
TG_1P5 and BG_1P5 Open
SLP_S5 = LOW, BOOT = 0 V,
TG_1P5 and BG_1P5 Open
SLP_S5 = HIGH, SLP_S3 = HIGH,
BOOT = 12 V, TG_1P5 and BG_1P5
Open
SLP_S5 = HIGH, SLP_S3 = LOW,
TG_1P5 and BG_1P5 Open
−
−
10
mA
V5VDUAL
VBOOT
−
−
4.5
10.5
5.0
12
5.5
13.2
V
V
Symbol
Test Conditions
Min
Typ
Max
Unit
S3 Mode Supply Current from 5VDUAL
S5 Mode Supply Current from 5VDUAL
S0 Mode Supply Current from BOOT
I5VDL_S3
I5VDL_S5
IBOOT_S0
−
−
−
−
−
−
5.0
1.0
25
mA
mA
mA
S3 Mode Supply Current from BOOT
UNDERVOLTAGE−MONITOR
5VDUAL UVLO Upper Threshold
5VDUAL UVLO Hysteresis
BOOT UVLO Upper Threshold
BOOT UVLO Hysteresis
THERMAL SHUTDOWN
Thermal Shutdown
Thermal Shutdown Hysteresis
DDQ SWITCHING REGULATOR
FBDDQ Feedback Voltage, Control Loop in
Regulation
Feedback Input Current
Oscillator Frequency in S0 Mode
Oscillator Frequency in S3 Mode
Oscillator Ramp Amplitude
Current Limit Blanking Time in S0 Mode
Current Limit Threshold Offset from 5VDUAL
Minimum Duty Cycle
Maximum Duty Cycle
Soft−Start Pin Current for DDQ
DDQ ERROR AMPLIFIER
DC Gain
Gain−Bandwidth Product
Slew Rate
IBOOT_S3
−
−
25
mA
V5VDLUV+
V5VDLhys
VBOOTUV+
VBOOThys
−
−
−
−
−
250
8.8
−
−
400
−
1.0
4.4
550
10.4
1.3
V
mV
V
V
Tsd
Tsdhys
(Note 3)
(Note 3)
−
−
145
25
−
−
°C
°C
VFBQ
IDDQFB
FDDQS0
FDDQS3
dVOSC
TDDQbk
VOCP
Dmin
Dmax
Iss1
T
A
= 25°C
T
A
= 0°C to 70°C
V(FBDDQ) = 1.3 V
−
−
(Note 3)
(Note 3)
(Note 3)
−
−
V(SS) = 0 V
1.178
1.166
−
217
434
−
400
0.8
0
−
3.0
1.190
−
−
250
500
1.3
−
−
−
−
4.0
1.202
1.214
1.0
283
566
−
−
−
−
100
−
V
mA
KHz
KHz
Vp−p
nS
V
%
%
mA
GAINDDQ
GBWDDQ
SRDDQ
(Note 3)
COMP PIN to GND = 220 nF,
1.0
W
in Series (Note 3)
COMP PIN TO GND = 10 pF
−
−
−
70
12
8.0
−
−
−
dB
MHz
V/uS
3. Guaranteed by design, not tested in production.
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