NCP436, NCP437
3A Ultra-Small Controlled
Load Switch with
Auto-Discharge Path
The NCP436 and NCP437 are very low Ron MOSFET controlled
by external logic pin, allowing optimization of battery life, and
portable device autonomy.
Indeed, due to a current consumption optimization with PMOS
structure, leakage currents are eliminated by isolating connected IC on
the battery when not used.
Output discharge path is also embedded to eliminate residual
voltages on the output rail for the NCP437 part only.
Proposed in a wide input voltage range from 1.0 V to 3.6 V, in a
small 1 x 1.5 mm WLCSP6, pitch 0.5 mm.
Features
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MARKING DIAGRAM
WLCSP6
CASE 567FH
A
Y
W
G
XXX
AYW
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
•
•
•
•
•
•
•
•
•
•
•
•
1.0 V − 3.6 V Operating Range
20 mW P MOSFET at 3.6 V
DC Current Up to 3 A
Output Auto−discharge
Active High EN Pin
WLCSP6 1 x 1.5 mm
These are Pb−Free Devices
PIN DIAGRAM
A
OUT
IN
B
OUT
IN
Typical Applications
Mobile Phones
Tablets
Digital Cameras
GPS
Portable Devices
C
GND
EN
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
V+
LS
NCP437
DCDC Converter
or
LDO
A2
B2
C2
IN
IN
EN
OUT
OUT
GND
A1
Platform IC’n
B1
ENx
C1
EN
0
Figure 1. Typical Application Circuit
©
Semiconductor Components Industries, LLC, 2014
1
April, 2014 − Rev. 1
Publication Order Number:
NCP436/D
NCP436, NCP437
PIN FUNCTION DESCRIPTION
Pin Name
IN
GND
EN
OUT
Pin Number
A2, B2
C1
C2
A1, B1
Type
POWER
POWER
INPUT
OUTPUT
Description
Load−switch input voltage; connect a 1
mF
or greater ceramic capacitor from IN to GND as
close as possible to the IC.
Ground connection.
Enable input, logic high turns on power switch.
Load−switch output; connect a 1
mF
ceramic capacitor from OUT to GND as close as
possible to the IC is recommended.
BLOCK DIAGRAM
IN: Pin A2, B2
OUT: Pin A1, B1
Gate driver and soft
start control
Control
logic
EN: Pin C2
EN block
Optional: NCP437
GND: Pin C1
Figure 2. Block Diagram
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2
NCP436, NCP437
MAXIMUM RATINGS
Symbol
V
EN ,
V
IN,
V
OUT
V
IN ,
V
OUT
T
J
ESD
HBM
ESD MM
ESD
CDM
LU
T
STG
MSL
IN, OUT, EN, Pins: (Note 1)
From IN to OUT Pins: Input/Output (Note 1)
Maximum Junction Temperature
Human Body Model (HBM) ESD Rating are (Notes 2 and 3)
Machine Model (MM) ESD Rating are (Notes 2 and 3)
Charge Device Model (CDM) ESD Rating are (Notes 2 and 3)
Latch−up Protection (Note )
− Pins IN, OUT, EN
Storage Temperature Range
Moisture Sensitivity (Note 2)
Rating
Value
−0.3 to + 4
0 to + 4
−40 to + 125
8000
250
2000
100
−40 to + 150
Level 1
Unit
V
V
°C
V
V
V
mA
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. According to JEDEC standard JESD22−A108.
2. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
3. This device series contains ESD protection and passes the following tests
Human Body Model (HBM)
±8.0
kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM)
±250
V per JEDEC standard: JESD22−A115 for all pins.
Charge Device Model (CDM)
±2.0
kV per JEDEC standard: JESD22−C101 for all pins.
4. Latch−up Current Maximum Rating:
±100
mA per JEDEC standard: JESD78 Class II.
OPERATING CONDITIONS
Symbol
V
IN
V
EN
T
A
T
J
C
IN
C
OUT
R
qJA
I
OUT
P
D
Parameter
Operational Power Supply
Enable Voltage
Ambient Temperature Range
Junction Temperature Range
Decoupling input capacitor
Decoupling output capacitor
Thermal Resistance Junction to Air
Maximum DC current
Power Dissipation Rating (Note 6)
T
A
≤
25°C
T
A
= 85°C
5. The R
qJA
is dependent of the PCB heat dissipation and thermal via.
6. The maximum power dissipation (
PD
) is given by the following formula:
WLCSP package
WLCSP package
0.66
0.26
WLCSP package (Note 5)
Conditions
Min
1.0
0
−40
−40
1
1
100
3
25
25
Typ
Max
3.6
3.6
+85
+125
°C
°C
mF
mF
°C/W
A
W
W
Unit
V
P
D
+
T
JMAX
*
T
A
R
qJA
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NCP436, NCP437
ELECTRICAL CHARACTERISTICS
Min and Max Limits apply for T
A
between −40°C to +85°C for
VIN
between 1.0 V to 3.6 V
(Unless otherwise noted). Typical values are referenced to T
A
= +25°C and V
IN
= 3.3 V (Unless otherwise noted).
Symbol
POWER SWITCH
I = 200 mA, 25°C
V
IN
= 3.6 V
I = 200 mA, T
A
= 85°C
T
J
= 125°C
I = 200 mA, 25°C
V
IN
= 2.5 V
Static drain−source on−state
resistance
V
IN
= 1.8 V
I = 200 mA, T
A
= 85°C
T
J
= 125°C
R
DS(on)
I = 200 mA, 25°C
I = 200 mA, Full Ta
T
J
= 125°C
I = 200 mA, 25°C
V
IN
= 1.2 V
I = 200 mA, Full Ta
T
J
= 125°C
V
IN
= 1.1 V
R
dis
V
IH
V
IL
Output discharge path
High−level input voltage
Low−level input voltage
V
IN
= 3.3 V
I = 200 mA, 25°C
EN = low
50
1.1
0.5
V
62
65
90
W
45
23
18
15
26
28
29
30
32
35
40
42
44
80
84
85
mW
Parameter
Conditions
Min
Typ
Max
Unit
QUIESCENT CURRENT
I
std
Iq
TIMINGS
T
EN
T
R
T
ON
T
DIS
T
F
Enable time
Output rise time
ON time (T
EN +
T
R
)
Disable time
Output fall time
V
IN
= 3.6 V
(Note 8)
R
L
= 25
W,
C
OUT
= 1
mF
R
L
= 25
W,
C
OUT
= 1
mF
R
L
= 25
W,
C
OUT
= 1
mF
R
L
= 25
W,
C
OUT
= 1
mF
NCP437. R
L
= 25
W,
C
OUT
= 1
mF
20
20
10
30
39
25
64
20
55
80
55
40
95
ms
Standby current
Quiescent current
V
IN
= 3.3 V
V
IN
= 3.3 V
EN = low, No load
EN = high, No load
0.01
0.2
0.6
0.6
mA
7. Guaranteed by design and characterization
8. Parameters are guaranteed for C
LOAD
and R
LOAD
connected to the OUT pin with respect to the ground
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NCP436, NCP437
TIMINGS
V
IN
EN
V
OUT
T
EN
T
R
T
DIS
T
OFF
T
F
T
ON
Figure 3. Enable, Rise and Fall Time
FUNCTIONAL DESCRIPTION
Overview
The NCP437 is a high side P channel MOSFET power
distribution switch designed to isolate ICs connected on the
battery in order to save energy. The part can be turned on,
with a wide range of battery from 1.0 V to 3.6 V.
Enable Input
The auto−discharge is activated when EN pin is set to low
level (disable state).
The discharge path (Pull down NMOS) stays activated as
long as EN pin is set at low level and V
IN
> 1.2 V.
In order to limit the current across the internal discharge
N−MOSFET, the typical value is set at 65
W.
IN and OUT, 1
mF,
at least, capacitors must be placed as
close as possible the part to for stability improvement.
C
IN
and C
OUT
Capacitors
Enable pin is an active high. The path is opened when EN
pin is tied low (disable), forcing P MOS switch off.
The IN/OUT path is activated with a minimum of V
IN
of
1.2 V and EN forced to high level.
Auto Discharge
NMOS FET is placed between the output pin and GND,
in order to discharge the application capacitor connected on
OUT pin.
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