NB3W1900L
3.3 V 100/133 MHz
Differential 1:19
HCSL-Compatible Push‐Pull
Clock ZDB/Fanout Buffer for
PCIe
[
Description
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The NB3W1900L differential clock buffers are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point-to-point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel
®
QuickPath Interconnect
(Intel QPI & UPI), PCIe Gen1/Gen2/Gen3/Gen4.The NB3W1900L
internal PLL is optimized to support 100 MHz and 133 MHz
frequency operation. The NB3W1900L is developed with the
low-power NMOS Push-Pull buffer type.
Features
1 72
QFN72
MN SUFFIX
CASE 485DK
MARKING DIAGRAM
1
NB3W
1900L
AWLYYWWG
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19 Low Power Differential Clock Output Pairs @
0.7
V
Output-to-Output Skew Performance: < 85 ps
Cycle-to-Cycle Jitter (PLL Mode): < 50ps
100 MHz and 133 MHz PLL Mode to Meet the Next Generation
PCIe Gen2/Gen3/Gen4 and Intel QPI & UPI Phase Jitter
Input-to-Output Delay Variation: < 50 ps
Fixed-Feedback for Lowest Input-to-Output Delay Variation
Spread Spectrum Compatible; Tracks Input Clock Spreading for Low
EMI
Individual OE Control via SMBus
Low-Power NMOS Push-Pull HCSL−Compatible Outputs
PLL Configurable for PLL Mode or Bypass Mode
(Fanout Operation)
SMBus Address Configurable to Allow Multiple Buffers in a Single
Control Network
Programmable PLL Bandwidth
Two Tri-level Addresses Selection (Nine SMBus Addresses)
QFN 72-pin Package, 10 mm
×
10 mm
These are Pb-Free Devices
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2017
1
January, 2018 − Rev. 3
Publication Order Number:
NB3W1900L/D
NB3W1900L
FBOUT_NC
FBOUT_NC#
SSC Compatible
PLL
DIF[18:0]
DIF[18:0]#
MUX
CLK_IN
CLK_IN#
100M_133M#
HBW_BYP_LBW#
SA_0
SA_1
PWRGD/PWRDN#
SDA
SCL
Control
Logic
Figure 1. Simplified Block Diagram
DIF18#
DIF17#
DIF16#
DIF15#
DIF14#
DIF13#
VDDIO
VDDIO
DIF18
DIF17
DIF16
DIF15
DIF14
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56
DIF13
55
GND
GND
GND
VDD
VDDA
GNDA
100M_133M#
HBW_BYP_LBW#
PWRGD/PWRDN#
GND
VDDR
CLK_IN
CLK_IN#
SA_0
SDA
SCL
SA_1
FBOUT_NC#
FBOUT_NC
GND
DIF0
DIF0#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
DIF1
DIF2
DIF3
VDD
DIF4
DIF5
DIF1#
DIF2#
DIF3#
DIF4#
DIF5#
DIF6
VDDIO
VDDIO
DIF6#
GND
GND
GND
54
53
52
51
50
49
48
47
DIF12#
DIF12
VDDIO
GND
DIF11#
DIF11
DIF10#
DIF10
GND
VDD
DIF9#
DIF9
DIF8#
DIF8
VDDIO
GND
DIF7#
DIF7
NB3W1900L
46
45
44
43
42
41
40
39
38
37
Figure 2. Pin Configuration
(Top View)
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2
NB3W1900L
Table 1. POWER DOWN PIN TABLE
Inputs
PWRGD/PWRDN#
0
1
CLK_IN /
CLK_IN#
X
Running
Control Bits
SMBus
EN Bit
X
0
1
DIFx / DIFx#
Low/Low
Low/Low
Running
Outputs
FBOUT_NC /
FBOUT_NC#
Low/Low
Running
Running
PLL Stage
OFF
ON
ON
Table 2. POWER CONNECTIONS
Pin Number
VDD
VDDIO
VDDR
7
1
28, 45, 64
21, 33, 40, 52, 57, 69
GND
6
2
16, 22, 27, 34, 39, 46, 51, 58, 63, 70
Description
Analog Input
Analog PLL
DIF clocks
Table 3. TRI-LEVEL INPUT THRESHOLDS
Level
Low
Mid
High
Voltage
< 0.8 V
1.2 < Vin < 1.8 V
Vin > 2.2 V
Table 5. PLL OPERATING MODE
HBW_BYP_LBW#
Low
Mid
High
NOTE:
PLL is OFF in Bypass
MODE
PLL Lo BW
Bypass
PLL Hi BW
Table 4. FUNCTIONALITY AT POWER-UP (PLL Mode)
CLK_IN
100M_133M#
1
0
MHz
100.00
133.33
DIFx
MHz
CLK_IN
CLK_IN
Table 6. MODE TRI−LEVEL INPUT THRESHOLD
Level
Low
Mid
High
Voltage
< 0.8 V
1.2 < Vin < 1.8 V
Vin > 2.2 V
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NB3W1900L
Table 7. NB3W1900L PIN DESCRIPTIONS
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
VDDA
GNDA
100M_133M#
HBW_BYP_LBW#
PWRGD/PWRDN#
GND
VDDR
CLK_IN
CLK_IN#
SA_0
SDA
SCL
SA_1
FBOUT_NC#
Type
PWR
GND
IN
IN
IN
GND
PWR
IN
IN
IN
I/O
IN
IN
OUT
3.3 V Power Supply for PLL core.
Ground for PLL core.
Input to select operating frequency.
See functionality table for definition.
Tri-level input to select High BW, Bypass or low BW mode.
See PLL operating mode table for definition.
Notifies device to sample latched inputs and start up on first high assertion, or exit
power down mode on subsequent assertions. Low enters power down mode.
Ground pin
3.3 V power for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately.
0.7 V differential true input
0.7 V differential complementary input
SMBus address bit. This is a tri-level input that works in conjunction with the SA_1
to decode 1 of 9 SMBus addresses.
Data pin of SMBus circuitry, 5 V tolerant
Clock pin of SMBus circuitry, 5 V tolerant
SMBus address bit. This is a tri-level input that works in conjunction with the SA_0
to decode 1 of 9 SMBus addresses.
Complementary half of differential feedback output. This pin should NOT be
connected to anything outside the chip. It exists to provide delay path matching to
get 0 ps propagation delay.
True half of differential feedback output. This pin should NOT be connected to
anything outside the chip. It exists to provide delay path matching to get 0
propagation delay.
Ground pin
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Power supply for differential outputs
Ground pin
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Ground pin
Power supply nominal 3.3 V
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Power supply for differential outputs
Ground pin
0.7 V differential true clock output
Description
15
FBOUT_NC
OUT
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
GND
DIF0
DIF0#
DIF1
DIF1#
VDDIO
GND
DIF2
DIF2#
DIF3
DIF3#
GND
VDD
DIF4
DIF4#
DIF5
DIF5#
VDDIO
GND
DIF6
GND
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
1. All VDD, VDDR, VDDIO,VDDA and GND pins must be externally connected to a power supply for proper operation.
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NB3W1900L
Table 7. NB3W1900L PIN DESCRIPTIONS
(continued)
Pin Number
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
EP
Pin Name
DIF6#
DIF7
DIF7#
GND
VDDIO
DIF8
DIF8#
DIF9
DIF9#
VDD
GND
DIF10
DIF10#
DIF11
DIF11#
GND
VDDIO
DIF12
DIF12#
DIF13
DIF13#
VDDIO
GND
DIF14
DIF14#
DIF15
DIF15#
GND
VDD
DIF16
DIF16#
DIF17
DIF17#
VDDIO
GND
DIF18
DIF18#
Exposed Pad
Type
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
Thermal
Description
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Ground pin
Power supply for differential outputs
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Power supply nominal 3.3 V
Ground pin
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Ground pin
Power supply for differential outputs
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Power supply for differential outputs
Ground pin
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Ground pin
Power supply nominal 3.3 V
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Power supply for differential outputs
Ground pin
0.7 V differential true clock output
0.7 V differential complementary clock output
The Exposed Pad (EP) on the QFN-72 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be
attached to a heat-sinking conduit. The pad is electrically connected to the die, and
must be electrically and thermally connected to GND on the PC board.
1. All VDD, VDDR, VDDIO,VDDA and GND pins must be externally connected to a power supply for proper operation.
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