NB3V110xC Series
3.3V/2.5V/1.8V LVCMOS
Low Skew Fanout Buffer
Family
Description
The NB3V110xC are a modular, high−performance, low−skew,
general purpose LVCMOS clock buffer family. The family of devices
is designed with a modular approach. Four different fan−out
variations, 1:2, 1:3, 1:4, 1:6 and 1:8, are available. All of the devices
are pin compatible to each other for easy handling. All family
members share the same high performing characteristics like low
additive jitter, low skew, and wide operating temperature range. The
NB3V110xC supports an asynchronous output enable control (OE)
which switches the outputs into a low state when OE is low. The
NB3V110xC devices operate in a 3.3 V, 2.5 V and 1.8 V environment
and are characterized for operation from −40°C to 105°C.
Features
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TSSOP−8
DT SUFFIX
CASE 948S
TSSOP−14
DT SUFFIX
CASE 948G
TSSOP−16
DT SUFFIX
CASE 948F
•
•
•
•
•
•
•
Operating Temperature Range: –40°C to 105°C
High−Performance 1:2, 1:3, 1:4, 1:6, 1:8 LVCMOS Clock Buffer
Available in 8−, 14−, 16−Pin TSSOP and WDFN8 Packages
Very Low Output−to−Output Skew < 50 ps
Very Low Additive Jitter < 200 fs
Supply Voltage: 3.3 V, 2.5 V or 1.8 V
f
max
= 250 MHz for 3.3 V; f
max
= 180 MHz for 2.5 V;
f
max
= 133 MHz for 1.8 V
•
These Devices are Pb−Free and are RoHS Compliant
BLOCK DIAGRAM
WDFN8, 2x2
MT SUFFIX
CASE 511AT
MARKING DIAGRAMS
8
14
10x
YWW
AG
1
TSSOP−8
1
TSSOP−14
1
1106
V
ALYWG
G
1
TSSOP−16
16
1108
V
ALYWG
G
CLKIN
LV
CMOS
LV
CMOS
Q0
0X MG
G
WDFN8
LV
CMOS
Q1
LV
CMOS
Q2
LV
CMOS
Q3
S
S
S
A
= Assembly Location
M
= Date Code
L
= Wafer Lot
Y
= Year
W, WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
LV
CMOS
OE
Qn
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 9 of this data sheet.
©
Semiconductor Components Industries, LLC, 2017
1
January, 2017 − Rev. 3
Publication Order Number:
NB3V1102C/D
NB3V110xC Series
CLKIN
CLKIN
OE
CLKIN
OE
Q0
GND
1
2
3
4
NB3V1102C
NB3V1103C
NB3V1104C
8
7
6
5
Q1
NC/Q3
GND
VDD
VDD
NC/Q2
Q4
5
6
7
4
NB3V1106C
11
10
9
8
Q2
GND
Q5
VDD
VDD
Q4
GND
Q6
5
6
7
8
Q0
1
2
3
14
13
12
Q1
Q3
VDD
OE
Q0
GND
1
2
3
4
NB3V1108C
12
11
10
9
16
15
14
13
Q1
Q3
VDD
Q2
GND
Q5
VDD
Q7
TSSOP−8 and WDFN8
GND
TSSOP−14
TSSOP−16
Figure 1. Pin Configuration
Table 1. PIN DESCRIPTION
LVCMOS Clock
Input
Devices
NB3V1102C
NB3V1103C
NB3V1104C
NB3V1106C
NB3V1108C
CLKIN
1
1
1
1
1
LVCMOS Clock
Output Enable
OE
2
2
2
2
2
LVCMOS Clock Output
Q0, Q1, ... Q7
3, 8
3, 8, 5
3, 8, 5, 7
3, 14, 11, 13, 6, 9
3, 16, 13, 15, 6, 11, 8, 9
Device
Supply Voltage
V
DD
6
6
6
5, 8, 12
5, 10, 14
Device
Ground
GND
4
4
4
4, 7, 10
4, 7, 12
NOTE: Pins not mentioned in the table are NC.
Table 2. OUTPUT LOGIC TABLE
INPUTS
CLKIN
X
L
H
OE
L
H
H
OUTPUTS
Qn
L
L
H
Table 3. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model (HBM) per ANSI/ESDA/JEDEC JS−001−2014
Charged Device Model (CDM) per ANSI/ESDA/JEDEC JS−002−2014
Value
5000
1500
Level 1
Unit
V
V
−
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
Meets or exceeds JEDEC Spec JESD78D (LU) IC Latchup Test
1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with a large copper heat spreader (20 mm
2
, 2 oz.)
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2
NB3V110xC Series
Table 4. ABSOLUTE MAXIMUM RATINGS
(Note 2)
Over operating free−air temperature range (unless otherwise noted)
Symbol
V
DD
V
IN
V
O
I
IN
I
O
q
JA
Supply Voltage Range
Input Voltage Range (Note 3)
Output Voltage Range (Note 3)
Input Current
Continuous Output Current
Thermal Resistance (Junction−to−Ambient)
TSSOP−8
TSSOP−14
TSSOP−16
WDFN8
q
JC
Thermal Resistance (Junction−to−Case top)
TSSOP−8
TSSOP−14
TSSOP−16
WDFN8
T
J
T
STG
Maximum Junction Temperature
Storage Temperature Range
Condition
Value
–0.5 to 4.6
–0.5 to V
DD
+ 0.5
–0.5 to V
DD
+ 0.5
±20
±50
151.2*
104*
32*
110**
190**
35
8.6
10
10
125
–65 to 150
°C
°C
°C/W
Unit
V
V
V
mA
mA
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with a large copper heat spreader (20 mm
2
, 2 oz.)
3. For additional information, see Application Note AND8003/D.
*JEDEC51.7 four layer PCB with 100 sqmm, 2 oz with two 80x80x1oz ground planes.
**JEDEC51.3 two layer PCB with 100 sqmm, 2 oz.
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3
NB3V110xC Series
Table 5. RECOMMENDED OPERATING CONDITIONS
Over operating free−air temperature range (unless otherwise noted)
Symbol
V
DD
Supply voltage range
Condition
3.3 V supply
2.5 V supply
1.8 V supply
V
IL
Low−level input voltage
V
DD
= 3.0 V to 3.6 V
V
DD
= 2.3 V to 2.7 V
V
DD
= 1.71 V to 1.89 V
V
IH
High−level input voltage
V
DD
= 3.0 V to 3.6 V
V
DD
= 2.3 V to 2.7 V
V
DD
= 1.71 V to 1.89 V
V
th
Input threshold voltage
V
DD
= 2.3 V to 3.6 V
V
DD
= 1.71 V to 1.89 V
t
r
/ t
f
t
w
Input slew rate (Note 4)
Minimum pulse width at CLKIN
V
DD
= 3.0 V to 3.6 V
V
DD
= 2.3 V to 2.7 V
V
DD
= 1.71 V to 1.89 V
f
CLK
LVCMOS clock Input Frequency
V
DD
= 3.0 V to 3.6 V
V
DD
= 2.3 V to 2.7 V
V
DD
= 1.71 V to 1.89 V
T
A
Operating free−air temperature
1
1.8
2.75
3.75
DC
DC
DC
–40
250
180
133
105
°C
MHz
V
DD
/2 +
600
V
DD
/2 +
400
0.7xV
DD
V
DD
/2
V
DD
/2
4
V
V
V
V/ns
ns
Min
3.0
2.3
1.71
Typ
3.3
2.5
1.8
Max
3.6
2.7
1.89
V
DD
/2 –
600
V
DD
/2 –
400
0.3xV
DD
V
mV
mV
Unit
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Guaranteed by Design.
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NB3V110xC Series
Table 6. DEVICE CHARACTERISTICS
Over recommended operating free−air temperature range (unless otherwise noted) (Note 5)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
OVERALL PARAMETERS FOR ALL VERSIONS
I
DD
Static device current
OE = V
DD
; CLKIN = 0 V or V
DD
; I
O
= 0 mA; V
DD
=
3.6 V
OE = V
DD
; CLKIN = 0 V or V
DD
; I
O
= 0 mA; V
DD
=
2.7 V
OE = V
DD
; CLKIN = 0 V or V
DD
; I
O
= 0 mA; V
DD
=
1.89 V
I
PD
Power down current
OE = 0 V; CLKIN = 0 V or V
DD
; I
O
= 0 mA; V
DD
=
3.6 V, 2.7 V or 1.89 V (For 1102C, 1103C, 1104C)
OE = 0 V; CLKIN = 0 V or V
DD
; I
O
= 0 mA; V
DD
=
3.6 V, 2.7 V or 1.89 V (For 1106C, 1108C)
C
PD
Power dissipation capacitance per out-
put (Note 6)
V
DD
= 3.3 V; f = 10 MHz
V
DD
= 2.5 V; f = 10 MHz
V
DD
= 1.8 V; f = 10 MHz
I
I
Input leakage current at OE
Input leakage current at CLKIN
Input leakage current at OE, CLKIN
R
OUT
Output impedance
V
I
= 0 V or V
DD
, V
DD
= 1.89 V
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 1.8 V
f
OUT
Output frequency
V
DD
= 3.0 V to 3.6 V
V
DD
= 2.3 V to 2.7 V
V
DD
= 1.71 V to 1.89 V
OUTPUT PARAMETERS FOR V
DD
= 3.3 V
+
0.3 V
V
OH
High−level output voltage
V
DD
= 3 V, I
OH
= –0.1 mA
V
DD
= 3 V, I
OH
= –8 mA
V
DD
= 3 V, I
OH
= –12 mA
V
OL
Low−level output voltage
V
DD
= 3 V, I
OL
= 0.1 mA
V
DD
= 3 V, I
OL
= 8 mA
V
DD
= 3 V, I
OL
= 12 mA
t
PLH
,
t
PHL
t
sk(o)
t
r
/t
f
t
DIS
t
EN
t
sk(p)
t
sk(pp)
T
jit(f)
Propagation delay (Note 7)
Output skew (Note 7)
Rise and fall time
Output disable time (Note 7)
Output enable time (Note 7)
Pulse skew; t
PLH(Qn)
– t
PHL(Qn)
(Note 8)
Part−to−part skew
Additive jitter rms
CLKIN to Qn
Equal load of each output 85°C
Equal load of each output 105°C
20%–80% (V
OH
− V
OL
)
OE to Qn
OE to Qn
To be measured with input duty cycle of 50%
Under equal operating conditions for two parts
12 kHz...20 MHz f
OUT
= 100 MHz
12 kHz...20 MHz f
OUT
= 156.25 MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All typical values are at respective nominal V
DD
.
For switching characteristics, outputs are terminated to 50
W
to V
DD
/2 (see Figure 2).
6. This is the formula for the power dissipation calculation.
Ptot = Pstat + Pdyn + PCload [W] P
stat
= V
DD
x I
DD
[W]
P
dyn
= C
PD
x V
DD
2 x ƒ x n [W]
P
Cload
= C
load
x V
DD
2 x ƒ x n [W]
n = Number of switching output pins
7. With rail to rail input clock.
8. t
sk(p)
depends on output rise− and fall−time (t
r
/t
f
). The output duty−cycle can be calculated: odc = (t
w(OUT)
±
t
sk(p)
)/t
period
; t
w(OUT)
is
pulse−width of ideal output waveform and tperiod is 1/f
OUT
.
0.12
0.8
2.9
2.5
2.2
0.1
0.5
0.8
2.0
50
60
0.8
6
6
180
0.5
100
ns
ns
ns
ps
ns
fs
ns
ps
V
V
DC
DC
DC
40
45
60
250
180
133
MHz
V
I
= 0 V or V
DD
, V
DD
= 3.6 V or 2.7 V
9
9
9
±
8
±
8
±
8
W
mA
0.2
0.2
0.2
60
75
pF
mA
mA
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