BelaSigna R261
Advanced Noise Reduction
Solution for Voice Capture
Devices
BELASIGNA
®
R261 is a complete system−on−chip (SoC) solution
that provides advanced dual−microphone noise reduction in voice
capture applications such as laptops, mobile phones, webcams, tablet
computers and other applications that will benefit from improved
voice clarity.
Featuring a novel approach to removing mechanical, stationary and
non−stationary noise, the chip preserves voice naturalness for greater
speech intelligibility even when the talker is further away or not
optimally aligned with microphones providing unmatched freedom of
movement for end−users. Designed to be compatible with a wide
range of codecs, baseband chips and microphones without the need for
calibration, BelaSigna R261 is easy to integrate, improving
manufacturers’ speed to market.
Additional features include the ability to customize multiple voice
capture modes and tune the algorithm to the unique needs of a
manufacturer’s device. The chip includes a highly optimized
DSP−based application controller with industry−leading energy
efficiency and is packaged in two highly compact 5.3 mm
2
WLCSPs
to fit into even the most sized−constrained architectures and allow the
use of the cheapest printed circuit board design technologies.
Key Features
Introduction
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WLCSP−30
W SUFFIX
CASE 567CT
WLCSP−26
W SUFFIX
CASE 567CY
MARKING DIAGRAMS
1
BR261
W30
ALYW
BR261
W30
W26
A
L
YW
1
BR261
W26
ALYW
Typical Applications
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•
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•
•
Notebook Computers
Mobile Phones
Tablet PCs
Webcams
Any Portable Audio Application with Voice Pick−up
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 31 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
November, 2012
−
Rev. 2
1
ÈÈ
ÈÈ
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•
•
•
•
•
•
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Advanced Two−Microphone Noise Reduction Algorithm
Preserves Voice Naturalness
Supports Close−Talk, Far−Talk and Custom Mode
Conference Mode enables 360 Degrees Voice Pick−up
Configurable Algorithm Performance
Ultra Low Power Consumption
Ultra Miniature Form Factor
Complete System−on−Chip (SoC)
Highly Flexible Clocking Architecture
Hardware Configuration Interfaces
Prototyping Tools
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
= BelaSigna R261
= 30−ball version
= 26−ball version
= Assembly Location
= Wafer Lot
= Date Code Year & Week
= Pb−Free Package
= A1 Corner Indicator
ORIENTATION
1
(Top View)
Publication Order Number:
BR261/D
BR261
W30
ALYW
BelaSigna R261
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply (Applies on VBAT, VBATRCVR and VDDO for “Max” and for
VSSA, VSSRCVR and VSSD for “Min”) (Note 1)
Digital input pin voltage
Operating temperature range
Storage temperature range
Min
−0.3
VSSA
−
0.3 V
−40
−40
Max
4.0
VDDO + 0.3 V
85
85
Unit
V
V
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Time limit at maximum voltage must be less than 100 ms.
NOTE: Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
This device series incorporates ESD protection and is tested by the following methods:
−
ESD Human Body Model (HBM) tested per AEC−Q100−002 (EIA/JESD22−A114)
−
ESD Machine Model (MM) tested per AEC−Q100−003 (EIA/JESD22−A115)
This device series incorporates latch−up immunity and is tested in accordance with JESD78:
Electrical Performance Specifications
Table 2. ELECTRICAL CHARACTERISTICS
(The typical parameters in Table 2 were measured at 20°C with a clean
3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified
for all process corners but not tested on every part.)
Parameter
OVERALL
Supply voltage
Maximum risetime
Average current consumption
VBAT
Between 0 V and 1.8 V
Active mode, VBAT = 3.3 V
Bypass mode, VBAT = 3.3 V
Lineout mode, VBAT = 3.3 V
Sleep mode, VBAT = 3.3 V
Peak active current
VREG (1
mF
External Capacitor)
Output voltage
PSRR
Load regulation
Load current
Line regulation
−1
VREG
Without load, or with micro-
phone attached (0 to 200
mA)
@ 1 kHz
@ 2 mA
0.95
54
5
6
2
1
1.00
1.05
V
dB
mV/mA
mA
mV/V
l
VBAT = 3.63 V
21
14
15
2.5
1.2
32
17
160
19
1.8
3.3
3.63
10
16
V
ms
mA
mA
mA
mA
mA
Symbol
Test Conditions / Notes
Min
Typ
Max
Unit
Screened
VDDA (1
mF
External Capacitor on VDDA + 100 nF External Capacitor on CAP0/CAP1)
Output voltage
PSRR
Load regulation
Load current
Line regulation
VDDD (1
mF
External Capacitor)
Output voltage
VDDD
1.62
1.70
1.98
V
l
−1
VDDA
Unloaded with VREG = 1 V
@ 1 kHz
@ 1 mA
1.8
45
80
140
1
2
2.0
2.1
V
dB
mV/mA
mA
mV/V
l
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BelaSigna R261
Table 2. ELECTRICAL CHARACTERISTICS
(continued) (The typical parameters in Table 2 were measured at 20°C with a clean
3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified
for all process corners but not tested on every part.)
Parameter
VMIC
Output voltage
VMIC = VREG
VMIC = VDDA
Load Regulation
VMIC = VREG
VMIC = VDDA
POWER ON RESET
POR Threshold
POR Release
(VBAT going up)
POR Activation
(VBAT going down)
Boot Time
NRST to DMIC active using
LSAD boot method
NRST to DMIC active using
EEPROM boot method
(default custom application)
INPUT STAGE
Sampling frequency
Analog input voltage
Vin
Vin
Preamplifier gain tolerance
Input impedance
Rin
Defined by ROM−based
application.
No preamp gain on AI1
and AI3
30 dB preamp gain by default
on MIC0 and MIC2
1 kHz
0 dB preamplifier gain,
MCLK = 1.28 MHz
All other gain settings
Line−Out
Input offset voltage
0 dB preamp gain
All other gains
Channel cross coupling
Analog Filter cut−off frequency
Any 2 channels
LPF enabled
LPF disabled
Analog Filter passband flatness
Analog filter stopband
attenuation
Digital Filter cut−off frequency
Digital Filter cut−off stopband
attenuation
Total Harmonic Distortion +
Noise (Peak value)
Dynamic Range
Equivalent Input Noise
THDN
DR
EIN
30 dB preamplifier gain
VBAT = 3.3 V
30 dB preamplifier gain
VBAT = 3.3 V
30 dB preamplifier gain
VBAT = 3.3 V
80
−64
−77
−68
−78
3
10
50
−1
60
8
1
−84
20
0
0
−2
220
510
5.20
16
2
63.25
2
254
585
5.35
7
0.6
−60
30
kHz
Vpp
mVpp
dB
kW
kW
kW
mV
mV
dB
kHz
kHz
dB
dB
kHz
dB
dB
dB
mV
l
1.52
1.52
1.60
1.60
16
100
1.71
1.65
V
V
ms
ms
l
l
0.95
1.8
1.00
2.0
25
100
1.05
2.1
40
150
V
V
mV/mA
mV/mA
l
l
Symbol
Test Conditions / Notes
Min
Typ
Max
Unit
Screened
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BelaSigna R261
Table 2. ELECTRICAL CHARACTERISTICS
(The typical parameters in Table 2 were measured at 20°C with a clean
3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified
for all process corners but not tested on every part.)
Parameter
DIGITAL MICROPHONE OUTPUT
DMIC input clock frequency
With presets 0 or 5 selected
on CONFIG_SEL (Note 2)
With preset 1 selected on
CONFIG_SEL (Note 2)
With preset 3 selected on
CONFIG_SEL (Note 2)
With preset 2 selected on
CONFIG_SEL (Note 2)
Clock duty cycle
Input clock jitter
Clock to output transition time
ANALOG OUTPUT STAGE
Signal Range
Vout
One single ended DAC used
Two DACs used as one
differential output
Attenuator gain tolerance
Output impedance
Rout
@ 12 dB output attenuation
@ 0 dB output attenuation
Channel cross coupling
Analog Filter cut−off frequency
LPF Enabled
LPF Disabled
Analog Filter passband flatness
Analog filter stopband
attenuation
Digital Filter cut−off frequency
Digital Filter cut−off stopband
attenuation
Total Harmonic Distortion +
Noise (Peak value)
Dynamic Range
Noise Floor
DIRECT DIGITAL OUTPUT (available only through custom mode)
Supply voltage
Signal Range
VBATRCVR
Vout
One Differential Output Driver
used @ 1 kHz
Single ended Output Driver
used @ 1 kHz
Output Impedance
Maximum Current
Total Harmonic Distortion +
Noise (Peak value)
THDN
−67
−71
Rout
Load between
1 mA and 30 mA @ 0°C
1.8
0
0
3.3
3.6
2*VBAT
RCVR
VBATRC
VR
4
90
V
Vpp
Vpp
W
mA
dB
l
THDN
DR
80
−62
−74
−68
−83
70
100
> 60 kHz
13.0
25
−1
90
8
0
0
−2
2
4
2
16
3
−65
13.5
26
1
Vpp
Vpp
dB
kW
kW
dB
kHz
kHz
dB
dB
kHz
dB
dB
dB
mV
l
l
l
l
DMIC_OUT
Any clock configuration
Maximum allowed jitter on the
DMIC_CLK
10
20
40
2.048
2.4
2.8
3.072
50
60
10
50
MHz
MHz
MHz
MHz
%
ns
ns
Symbol
Test Conditions / Notes
Min
Typ
Max
Unit
Screened
2. Many other clock frequencies are available through custom configuration of the internal PLL and clocking subsystem. See later in this
document and in the BelaSigna R261 Configuration and Communications Guide for more information on custom mode usage.
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BelaSigna R261
Table 2. ELECTRICAL CHARACTERISTICS
(continued) (The typical parameters in Table 2 were measured at 20°C with a clean
3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified
for all process corners but not tested on every part.)
Parameter
Symbol
Test Conditions / Notes
Min
Typ
Max
Unit
Screened
DIRECT DIGITAL OUTPUT (available only through custom mode)
Dynamic Range
Noise Floor
LOW−SPEED A/D
Input voltage
Sampling frequency
Input impedance
Offset error
Gain error
INL
DNL
DIGITAL PADS (VDDO = 1.8 V)
Voltage level for Low input
Voltage level for High input
Pull−up resistance
Pull−down resistance
Rise and Fall Time
DIGITAL PADS (VDDO = 3.3 V)
Voltage level for Low input
Voltage level for High input
Pull−up resistance
Pull−down resistance
Rise and Fall Time
DIGITAL PADS (Common parameters)
Drive Strength
ESD Immunity
HBM
MM
Latch−up Immunity
CLOCKING CIRCUITRY
External clock frequency
EXT_CLK
EXT_CLK
Reference clock duty cycle
External Input clock jitter
I
2
C INTERFACE
Maximum speed
400
kbps
Maximum allowed jitter on
EXT_CLK
With preset 6 selected on
CONFIG_SEL (Note 2)
With presets 4 or 7 selected
on CONFIG_SEL (Note 2)
40
19.2
26
50
60
10
MHz
MHz
%
ns
Human Body Model
Machine Model
25°C, V < GNDO, V > VDDO
2.5
200
150
12
mA
kV
V
mA
20 pF load
VIL
VIH
−0.3
1.8
34
29
1.0
46
56
1.5
0.8
3.6
74
86
2.0
V
V
kW
kW
ns
l
l
l
l
20 pF load
VIL
VIH
−0.3
1.30
63
87
2
114
153
3
0.4
1.98
162
215
5
V
V
kW
kW
ns
INL
DNL
Rin
Input at VREG
Input to VSSA or 2*VREG
VDDO > 2.15 V
VDDO > 2.15 V
Vin
For each LSAD channel
0
1.6
1
−10
−10
−4
−2
10
10
4
2
MCLK/28
2*VREG
4.8
V
kHz
MW
LSB
LSB
LSB
LSB
DR
−80
−86
50
75
dB
mV
l
l
2. Many other clock frequencies are available through custom configuration of the internal PLL and clocking subsystem. See later in this
document and in the BelaSigna R261 Configuration and Communications Guide for more information on custom mode usage.
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