NCV8851-1
Automotive Grade
Synchronous Buck
Controller
The NCV8851−1 is an adjustable output, synchronous buck
controller, which drives dual N−channel MOSFETs, ideal for high
power applications. Average current mode control is employed for
very fast transient response and tight regulation over wide input
voltage and output load ranges. The IC incorporates an internal fixed
6.0 V low−dropout linear regulator (LDO), which supplies charge to
the switch mode power supply’s (SMPS) bottom gate driver, limiting
the power lost to excess gate drive. The IC is designed for operation
over a wide input voltage range (4.5 V to 40 V) and is capable of 10 to
1 voltage conversion at 500 kHz.
Additional controller features include undervoltage lockout,
internal soft−start, low quiescent current sleep mode, programmable
frequency, SYNC function, average current limiting, cycle−by−cycle
overcurrent protection and thermal shutdown.
Features
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TSSOP−20
SUFFIX DB
CASE 948E
MARKING DIAGRAM
•
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•
•
•
•
•
•
•
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Average Current Mode Control
0.8 V
±2%
Reference Voltage
Wide Input Voltage Range of 4.5 V to 40 V
Operates through Load Dump Conditions
6.0 V Low−dropout Linear Regulator (LDO)
Input UVLO (Undervoltage Lockout)
Internal Soft−start
1.0
mA
Maximum Quiescent Current in Sleep Mode
Adaptive Non−overlap Circuitry
180 ns Minimum High−side Gate Off−time
Programmable Fixed Frequency – 170 kHz to 500 kHz
External Clock Synchronization up to 600 kHz
Average Current Limiting (ACL)
Cycle−by−Cycle Overcurrent Protection (OCP)
Thermal Shutdown (TSD)
This is a Pb−Free Device
V88
51−1
ALYWG
G
V8851−1 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping
†
2500 / Tape &
Reel
NCV8851−1DBR2G TSSOP−20
(Pb−Free)
Applications
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
•
Automotive Systems Requiring High Current
•
Pre−regulated Supply for Low−voltage SMPSs and LDOs
©
Semiconductor Components Industries, LLC, 2014
1
November, 2014 − Rev. 2
Publication Order Number:
NCV8851−1/D
NCV8851−1
V
IN
12
EN 11
V
IN_IC
SYNC
3
1
Fixed−Frequency
Oscillator
Ramp
Clock
Max
Duty
S
Enable
Fault
Logic
UVLO
TSD
LDO
I
LIMIT
+
V
REF
9
6V
OUT
LDO
Enable
Fault
Soft Start
V
SS
4
5
BST
GH
V
SW
R
OSC
20
Min
On
R
Q Time
Reset
Dominant
PWM
Fault
C
COMP
15
OCP
CEA
C
FB
16
CS
OUT
17
V
COMP
14
V
FB
13
V
CLAMP
VEA
+
V
REF
V
OCP
+
BST
Q
6
Nonoverlap
6V
OUT
7
8
2
GL
PGND
V
IN_CS
19 CSP
CSA
18 CSN
+
V
ACL
V
SS
ACL
10 AGND
Figure 1. Functional Block Diagram
V
IN
V
IN
EN
V
IN_IC
SYNC
R
OSC
12
11
3
1
20
9
6V
OUT
D
BST
+
+
4
5
6
7
8
BST
Q1
GH
V
SW
Q2
GL
PGND
V
IN_CS
CSP
CSN
V
FB
C
V2
V
COMP
R
V1
C
V1
V
IN
−
C
BST
L
R
S
C
+
V
OUT
+
R
OSC
C
COMP
C
C1
R
C1
C
FB
R
C2
CS
OUT
2
15
19
18
13
16
17
10
AGND
14
−
R
F1
C
C2
R
F0
Figure 2. Application Schematic
Note: This part is recommended for synchronous use only.
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2
NCV8851−1
PACKAGE PIN DESCRIPTIONS − 20 Lead TSSOP
Package Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Symbol
SYNC
V
IN_CS
V
IN_IC
BST
GH
V
SW
GL
PGND
6V
OUT
AGND
EN
V
IN
V
FB
V
COMP
C
COMP
C
FB
CS
OUT
CSN
CSP
R
OSC
External clock synchronization input.
Supply input for the internal current sense amplifier.
Supply input for internal logic and analog circuitry.
Supply input for the floating top gate driver. An external diode, D
BST
, from 6V
OUT
and a
0.1
mF
to 1
mF
capacitor, C
BST
, to V
SW
forms a boost circuit.
Gate driver output for the external high−side NMOS FET.
Switch−node. This pin connects to the source of the high−side MOSFET and drain of the
low−side MOSFET. This pin serves as the switch output to the inductor.
Gate driver output for the external low−side NMOS FET.
Power Ground. Ground reference for the high−current path including the NMOS FETs and
output capacitor.
Output of internal fixed 6.0 V LDO.
Analog Ground. Ground reference for the internal logic and analog circuitry as well as R
OSC
and the compensators.
Enable input. When disabled, the LDO, internal logic and analog circuitry and gate drivers
enter sleep mode, drawing under 1
mA.
Supply input for the SMPS.
SMPS’s voltage feedback. Inverting input to the voltage error amplifier. Connect to V
OUT
through a resistive divider.
SMPS’s voltage error amplifier output and non−inverting input to the current error amplifier.
SMPS’s current error amplifier output and inverting input to the PWM comparator.
SMPS’s current feedback. Inverting input to the current error amplifier.
Single−ended output of the differential current sense amplifier. Connect to C
FB
through a
resistor. Non−inverting input to the cycle−by−cycle overcurrent comparator.
Differential current sense amplifier inverting input.
Differential current sense amplifier non−inverting input.
Oscillator’s frequency adjust pin. Resistor to ground sets the oscillator frequency.
Function
MAXIMUM RATINGS
(Voltages are with respect to AGND unless otherwise indicated.)
Rating
Dc Supply Voltage (V
IN
)
Peak Transient Voltage (Load Dump)
Dc Supply Voltage (V
IN_CS
)
Dc Supply Voltage (V
IN_IC
)
Pin Voltage (V
SW
)
t
≤
50 ns
Pin Voltage (BST, GH)
Pin Voltage (GL)
Pin Voltage (EN)
Pin Voltage (CSP, CSN)
Pin Voltage (V
FB
, V
COMP
, CS
OUT
, C
FB
, C
COMP
, SYNC, R
OSC
, 6V
OUT
)
Pin Voltage (PGND)
Operating Junction Temperature
Storage Temperature Range
Peak Reflow Soldering Temperature: Lead−free 60 to 150 seconds at 217°C
Value
−0.3 to 40
45
46
6.5
−0.7 to 40.7
−2
46 wrt PGND
7 wrt V
SW
−0.3 to 7 wrt PGND
−0.3 to 40
−0.3 to 10
−0.3 to 7
−0.3 to 0.3
−40 to 150
−65 to 150
265 peak
Unit
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
NCV8851−1
ATTRIBUTES
Characteristic
ESD Capability
Human Body Model (Boost, V
IN_CS
)
Human Body Model (All Others)
Machine Model
Charge Device Model
Package Thermal Resistance
Junction–to–Ambient, R
qJA
(Note 1)
Junction–to–Ambient, R
qJA
(Note 2)
1. 50 mm
2
, 1.0 oz copper on FR4 board.
2. 500 mm
2,
1.0 oz copper on FR4 board.
Value
≥
1.0 kV
≥
1.5 kV
≥
200 V
≥
1.0 kV
156°C/W
108°C/W
ELECTRICAL CHARACTERISTICS
(−40°C < T
J
< 150°C, 4.5 V < V
IN
< 40 V, 4.5 V < BST < 46 V, R
OSC
= 51.1 kW, unless otherwise specified)
Characteristic
GENERAL
Quiescent Current
(I
VIN
+ I
VIN_CS
+ I
BST
)
V
IN
= 13.2 V, EN = 0 V, Sleep Mode
−40°C < T
A
< 125°C
V
IN
= 13.2 V, V
FB
= 1 V
EN = 5 V, No Switching
V
IN
= 13.2 V, V
FB
= 0 V
EN = 5 V, Switching
LDO Current
Thermal Shutdown
Thermal Shutdown Hysteresis
Undervoltage Lockout (V
IN_IC
)
Undervoltage Lockout Hysteresis
SWITCHING REGULATOR
Reference Voltage
Minimum GH Off Time
Minimum GH Pulse Width
OSCILLATOR
Switching Frequency
R
OSC
= 51.1 kW
R
OSC
= 23.2 kW
R
OSC
= 16.2 kW
153
306
425
0.9
170
360
500
1.1
187
414
575
1.3
kHz
kHz
kHz
V
Static Operating
0.784
110
−
0.8
180
140
0.816
250
200
V
ns
ns
V
IN
= 13.2 V, V
FB
= 0 V, EN = 5 V
Switching, 3.3 nF on GH and GL
Guaranteed by Design
Guaranteed by Design
V
IN_IC
increasing
−
−
−
−
150
−
4.1
50
−
2.0
3.2
10
180
10
4.3
125
1
3.0
5.0
20
210
20
4.5
200
mA
mA
mA
mA
°C
°C
V
mV
Conditions
Min
Typ
Max
Unit
Ramp Voltage Amplitude
VOLTAGE ERROR AMPLIFIER
DC Gain
Gain−Bandwidth Product
Charge Currents
Guaranteed by Design
Guaranteed by Design
Source, V
COMP
= 0 V
Sink, V
COMP
= 1.75 V
FB Bias Current
CURRENT SENSE AMPLIFIER
Common−Mode Range
Amplifier Gain
0
≤
(CSP−CSN)
≤
100 mV
0 V
≤
CSN
≤
10.0 V
Guaranteed by Design
70
8.0
2
1.3
−
73
10
4
3
0.1
−
−
−
−
1.0
dB
MHz
mA
mA
mA
0
−
−
1
10.0
−
V
V/V
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NCV8851−1
ELECTRICAL CHARACTERISTICS
(−40°C < T
J
< 150°C, 4.5 V < V
IN
< 40 V, 4.5 V < BST < 46 V, R
OSC
= 51.1 kW, unless otherwise specified)
Characteristic
CURRENT ERROR AMPLIFIER
DC Gain
Gain−Bandwidth Product
Charge Currents
Guaranteed by Design
Guaranteed by Design
Source, C
COMP
= 1.75 V
Sink, C
COMP
= 1.75 V
FB Bias Current
Clamping Voltage
CURRENT LIMIT
Average Current Limit Threshold
Cycle−by−Cycle Current Limit
Threshold Voltage
Cycle−by−Cycle Current Limit
Response Time
Cycle−by−Cycle and Average Cur-
rent Limit Threshold Difference
SYNC
SYNC Frequency Range
SYNC Pin Bias Current
SYNC Threshold Voltage
6.0 V LDO
Output Voltage
Dropout Voltage
Current Limit
GATE DRIVERS
GH Sink Current
GH Source Current
GL Sink Current
GL Source Current
GH to GL Delay
GL to GH Delay
SOFT START
Time
ENABLE (EN)
Input Threshold
Input Current
Minimum Disable Time
Logic Low
Logic High
EN = 2.0 V
−
2.0
−
−
−
−
3.0
−
0.8
−
10
20
V
mA
ms
F
SW
= 170 kHz
−
14
−
ms
V
GH
= 2 V, V
IN_IC
= 6 V, Guaranteed by Design
V
GH
= 4 V, V
IN_IC
= 6 V, Guaranteed by Design
V
IN_IC
= 6 V
V
GL
= 1.0 V
Guaranteed by Design
V
IN
= 13.2 V
V
IN
= 13.2 V
−
−
−
−
−
−
1.5
1.5
1.5
1.5
40
40
−
−
−
−
70
70
A
A
A
A
ns
ns
I
OUT
= 20 mA
I
OUT
= 20 mA
5.8
−
30
6.0
−
75
6.2
200
120
V
mV
mA
V
SYNC
= 0 V
V
SYNC
= 5.0 V
Logic Low
Logic High
F
SW
−
−
−
2.0
−
0.1
10
−
−
600
0.2
20
0.8
−
kHz
mA
V
Guaranteed by Design
1.2 V
≤
CSN
≤
10.0 V
80
115
−
20
100
165
200
−
125
215
−
−
mV
mV
ns
mV
Guaranteed by Design
70
8.0
2
1.3
−
2.7
73
10
4
3
0.1
3.5
−
−
−
−
1.0
−
dB
MHz
mA
mA
mA
V
Conditions
Min
Typ
Max
Unit
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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