NCL30086
Analog/Digital Dimmable
Power Factor Corrected
Quasi-Resonant Primary
Side Current-Mode
Controller for LED Lighting
The NCL30086 is a power factor corrected flyback controller
targeting isolated and non−isolated “Smart−dimmable” constant
current LED drivers. The controller operates in a quasi−resonant mode
to provide optimal efficiency. The current control algorithm supports
flyback, buck−boost, and SEPIC topologies. Thanks to a novel control
method, the device is able to tightly regulate a constant LED current
from the primary side. This removes the need for secondary side
feedback circuitry, biasing and an optocoupler.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device is specifically intended for very compact space
efficient designs and supports analog and PWM dimming with a
dedicated dimming input intended to control the average LED current. To
ensure reliable operation at elevated temperatures, a user configurable
current foldback circuit is also provided. The NCL30086 is housed in
the SOIC10 which has the same body size as a standard SOIC8.
Features
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SOIC−10
CASE 751BQ
MARKING DIAGRAM
L30086x
ALYW
G
•
•
•
•
•
•
•
•
•
•
L30086x = Specific Device Code
x = A, B, C, D
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb-Free Package
Quasi−resonant Peak Current−mode Control Operation
Constant Current Control with Primary Side Feedback
Tight LED Constant Current Regulation of
±2%
Typical
Power Factor Correction
Analog or PWM dimming
Line Feedforward for Enhanced Regulation Accuracy
Low Start−up Current (10
mA
typ.)
Wide V
cc
Range
300 mA / 500 mA Totem Pole Driver with 12 V Gate Clamp
Robust Protection Features
♦
Brown−Out Detection
♦
OVP on V
CC
♦
Programmable Over Voltage / LED Open Circuit
Protection
♦
Cycle−by−cycle Peak Current Limit
♦
Winding Short Circuit Protection
♦
Secondary Diode Short Protection
♦
Output Short Circuit Protection
♦
Current Sense (CS) Short Detection
♦
User programmable NTC Based Thermal Foldback
♦
Thermal Shutdown
PIN CONNECTIONS
DIM
ZCD
VS
COMP
SD
(Top View)
1
NC
V
CC
DRV
GND
CS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 27 of this data sheet.
•
−40 to 125°C Operating Junction Temperature
•
Pb−Free, Halide−Free Product
•
Four Versions: NCL30086A, B, C and D (See Table 1)
Typical Applications
•
•
•
•
Integral LED Bulbs
LED Light Engines
LED Driver Power Supplies
Smart LED Lighting Applications
©
Semiconductor Components Industries, LLC, 2015
1
February, 2015 − Rev. 2
Publication Order Number:
NCL30086/D
NCL30086
.
Aux
.
.
V
DIM
NCL30086
1
2
3
4
5
10
9
8
7
6
R
sense
Figure 1. Typical Application Schematic in a Flyback Converter
.
Aux
.
V
DIM
NCL30086
1
2
3
4
5
10
9
8
7
6
R
sense
Figure 2. Typical Application Schematic in a Buck−Boost Converter
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NCL30086
Table 1. FOUR NCL30086 VERSIONS
Part Number
Protection Mode
Current Regulation
Reference Voltage
(V
REF
)
Recommended for (*):
Isolated converters.
Non−isolated converters with
NCL30086A
Latching−off
250 mV
V
out
v
2
@
(V
in,rms
)
LL
Isolated converters.
Non−isolated converters with
NCL30086B
Auto−recovery
250 mV
V
out
v
2
@
(V
in,rms
)
LL
Non−isolated converters with
NCL30086C
Latching−off
200 mV
V
out
u
2
@
(V
in,rms
)
LL
Non−isolated converters with
NCL30086D
Auto−recovery
200 mV
V
out
u
2
@
(V
in,rms
)
LL
*(V
in,rms
)
LL
designates the lowest line rms voltage. Refer to ANDxxxx/D for more details.
(http://www.onsemi.com/pub_link/Collateral/ANDxxxx−D.PDF).
Table 2. PIN FUNCTION DESCRIPTION
Pin No
1
Pin Name
DIM
Function
Analog / PWM Dimming
Pin Description
This pin is used for analog or PWM dimming control. An analog signal that can be
varied between V
DIM0
and V
DIM100
or a PWM signal can be used to adjust the
LED current.
Connected to the auxiliary winding, this pin detects the core reset event.
This pin monitors the input voltage rail for:
Power Factor Correction
Valley lockout
Brownout Detection
This pin receives a filtering capacitor for power factor correction. Typical values
ranges from 1 − 4.7
mF.
Connecting an NTC to this pin allows the user to program thermal current fold-
back threshold and slope. A Zener diode can also be used to pull−up the pin and
stop the controller for adjustable OVP protection.
This pin monitors the primary peak current.
Controller ground pin.
The driver’s output to an external MOSFET
This pin is the positive supply of the IC. The circuit starts to operate when
V
CC
exceeds 18 V and turns off when
V
CC
goes below 8.8 V (typical values). After
start−up, the operating range is 9.4 V up to 26 V (V
CC
(OVP )
minimum level).
−
2
3
ZCD
VS
Zero Crossing Detection
Input Voltage Sensing
4
5
COMP
SD
Filtering Capacitor
Thermal Foldback and
Shutdown
Current Sense
−
Driver Output
IC Supply Pin
6
7
8
9
CS
GND
DRV
V
CC
10
NC
−
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NCL30086
Internal Circuit Architecture
Enable
Over Voltage Protection
(Auto−recovery or Latched)
STOP
OFF
V
DD
V
REF
Aux_SCP
Fault
Management
UVLO
Latch
VCC
VCC Management
Over Temp. Protection
(Auto−recovery or Latched)
Internal
Thermal
Shutdown
SD
VCC_max
WOD_SCP
BO_NOK
Thermal
Foldback
V
TF
VCC Over Voltage
Protection
DRV
FF_mode
V
VS
VCC
ZCD
Zero Crossing Detection Logic
(ZCD Blanking, Time−Out, ...)
Aux. Winding Short Circuit Prot.
Aux_SCP
Valley Selection
Frequency Foldback
FF_mode
Clamp
Circuit
S
CS_ok
Q
Q
DRV
V
VS
R
Line
feed−forward
STOP
V
VS
DIM_disable
V
REFX
GND
CS
Leading
Edge
Blanking
Power Factor and
Constant−Current
Control
DIM_disable
CS_reset
Maximum
on time
STOP
Ipkmax
t
on,max
COMP
Max. Peak
Current
Limit
Ipkmax
V
VS
BO_NOK
Brown−Out
CS_ok
VS
CS Short
Protection
UVLO
t
on,max
V
REFX
V
REF
DIM_disable
DIM
Winding and
Output diode
Short Circuit
Protection
WOD_SCP
Dimming
control
V
TF
Figure 3. Internal Circuit Architecture
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NCL30086
Table 3. MAXIMUM RATINGS TABLE(S)
Symbol
V
CC(MAX)
I
CC(MAX)
V
DRV(MAX)
I
DRV(MAX)
V
MAX
I
MAX
R
θJ−A
T
J(MAX)
Rating
Maximum Power Supply voltage, V
CC
pin, continuous voltage
Maximum current for V
CC
pin
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
Maximum voltage on low power pins (except DRV and V
CC
pins)
Current range for low power pins (except DRV and V
CC
pins)
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
ESD Capability, HBM model (Note 3)
ESD Capability, MM model (Note 3)
ESD Capability, CDM model (Note 3)
Value
−0.3 to 30
Internally limited
−0.3, V
DRV
(Note 1)
−300, +500
−0.3, 5.5 (Notes 2 and 5)
−2, +5
180
150
−40 to +125
−60 to +150
3.5
250
2
Unit
V
mA
V
mA
V
mA
°C/W
°C
°C
°C
kV
V
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
DRV
is the DRV clamp voltage V
DRV(high)
when V
CC
is higher than V
DRV(high)
. V
DRV
is V
CC
otherwise.
2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5−V Zener diode. More positive and negative voltages can
be applied if the pin current stays within the −2 mA / 5 mA range.
3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,
Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.
4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds
±100
mA.
5.
Recommended maximum V
S
voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the V
S
pin recommended range.
Table 4. ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: For typical values T
J
= 25°C, V
CC
= 12 V, V
ZCD
= 0 V,
V
CS
= 0 V, V
SD
= 1.5 V) For min/max values T
J
= −40°C to +125°C, V
CC
= 12 V)
Description
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis V
CC(on)
– V
CC(off)
Internal logic reset
V
CC
Over Voltage Protection Threshold
V
CC(off)
noise filter
V
CC(reset)
noise filter
Startup current
Startup current in fault mode
Supply Current
Device Disabled/Fault
Device Enabled/No output load on DRV pin
Device Switching
CURRENT SENSE
Maximum Internal current limit
Leading Edge Blanking Duration for V
ILIM
Propagation delay from current detection to gate
off−state
V
ILIM
t
LEB
t
ILIM
0.95
240
−
1.00
300
100
1.05
360
150
V
ns
ns
V
CC
> V
CC(off)
F
sw
= 65 kHz
C
DRV
= 470 pF, F
sw
= 65 kHz
V
V
CC
rising
V
CC
rising
V
CC
falling
V
CC(on)
V
CC(off)
V
CC(HYS)
V
CC(reset)
V
CC(OVP)
t
VCC(off)
t
VCC(reset)
I
CC(start)
I
CC(Fault)
I
CC1
I
CC2
I
CC3
0.8
–
−
16.0
8.2
8
4
25.5
−
−
−
18.0
8.8
−
5
26.8
5
20
13
58
1.0
2.6
3.0
20.0
9.4
−
6
28.5
−
−
30
75
1.2
4.0
4.5
V
ms
mA
mA
mA
Test Condition
Symbol
Min
Typ
Max
Unit
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters R
TF(start)
, R
TF(stop)
, R
OTP(off)
and R
OTP(on)
give the resistance the
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V
CC
reaches V
CC(on)
, the controller blanks OTP for more than 250
ms
to avoid detecting an OTP fault by allowing the
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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