SN74LS161A, SN74LS163A
BCD Decade Counters/
4−Bit Binary Counters
The LS161A/163A are high-speed 4-bit synchronous counters.
They are edge-triggered, synchronously presettable, and cascadable
MSI building blocks for counting, memory addressing, frequency
division and other applications. The LS161A and LS163A count
modulo 16 (binary).
The LS161A has an asynchronous Master Reset (Clear) input that
overrides, and is independent of, the clock and all other control inputs.
The LS163A has a Synchronous Reset (Clear) input that overrides all
other control inputs, but is active only during the rising clock edge.
Binary (Modulo 16)
Asynchronous Reset
Synchronous Reset
LS161A
LS163A
16
1
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LOW
POWER
SCHOTTKY
PLASTIC
N SUFFIX
CASE 648
•
•
•
•
•
•
Synchronous Counting and Loading
Two Count Enable Inputs for High Speed Synchronous Expansion
Terminal Count Fully Decoded
Edge-Triggered Operation
Typical Count Rate of 35 MHz
ESD > 3500 Volts
16
1
SOIC
D SUFFIX
CASE 751B
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current
−
High
Output Current
−
Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
−0.4
8.0
Unit
V
°C
mA
mA
16
1
SOEIAJ
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
SN74LS161AN
SN74LS161AD
SN74LS161ADR2
SN74LS161AM
SN74LS161AMEL
SN74LS163AN
SN74LS163AD
SN74LS163ADR2
SN74LS163AM
SN74LS163AMEL
Package
16 Pin DIP
SOIC−16
SOIC−16
SOEIAJ−16
SOEIAJ−16
16 Pin DIP
SOIC−16
SOIC−16
SOEIAJ−16
SOEIAJ−16
Shipping
2000 Units/Box
38 Units/Rail
2500/Tape & Reel
See Note 1
See Note 1
2000 Units/Box
38 Units/Rail
2500/Tape & Reel
See Note 1
See Note 1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
©
Semiconductor Components Industries, LLC, 2006
July, 2006
−
Rev. 2
1
Publication Order Number:
SN74LS161A/D
SN74LS161A, SN74LS163A
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
TC
15
Q
0
14
Q
1
13
Q
2
12
Q
3
11
CET
10
PE
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
*MR for LS161A
*SR for LS163A
1
*R
2
CP
3
P
0
4
P
1
5
P
2
6
P
3
8
7
CEP GND
LOADING
(Note a)
PIN NAMES
PE
P
0
− P
3
CEP
CET
CP
MR
SR
Q
0
− Q
3
TC
Parallel Enable (Active LOW) Input
Parallel Inputs
Count Enable Parallel Input
Count Enable Trickle Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Synchronous Reset (Active LOW) Input
Parallel Outputs
Terminal Count Output
HIGH
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
10 U.L.
10 U.L.
LOW
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA
HIGH/1.6 mA LOW.
LOGIC SYMBOL
9
3
4
5
6
7
10
2
PE P
0
P
1
P
2
P
3
CEP
CET
CP
TC
15
*R Q
0
Q
1
Q
2
Q
3
1 14 13 12 11
V
CC
= PIN 16
GND = PIN 8
*MR for LS161A
*SR for LS163A
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2
SN74LS161A, SN74LS163A
STATE DIAGRAM
LS161A
•
LS163A
0
1
2
3
4
LOGIC EQUATIONS
Count Enable = CEP
•
CET
•
PE
TC for LS161A & LS163A = CET
•
Q
0
•
Q
1
•
Q
2
•
Q
3
Preset = PE
•
CP + (rising clock edge)
Reset = MR (LS161A)
Reset = SR
•
CP + (rising clock edge)
Reset =
(LS163A)
15
5
14
6
13
7
12
11
10
9
8
FUNCTIONAL DESCRIPTION
The LS161A/163A are 4-bit synchronous counters with
a synchronous Parallel Enable (Load) feature. The counters
consist of four edge-triggered D flip-flops with the
appropriate data routing networks feeding the D inputs. All
changes of the Q outputs (except due to the asynchronous
Master Reset in the LS161A) occur as a result of, and
synchronous with, the LOW to HIGH transition of the Clock
input (CP). As long as the set-up time requirements are met,
there are no special timing or activity constraints on any of
the mode control or data inputs.
Three control inputs — Parallel Enable (PE), Count
Enable Parallel (CEP) and Count Enable Trickle (CET) —
select the mode of operation as shown in the tables below.
The Count Mode is enabled when the CEP, CET, and PE
inputs are HIGH. When the PE is LOW, the counters will
synchronously load the data from the parallel inputs into the
flip-flops on the LOW to HIGH transition of the clock.
Either the CEP or CET can be used to inhibit the count
sequence. With the PE held HIGH, a LOW on either the CEP
or CET inputs at least one set-up time prior to the LOW to
HIGH clock transition will cause the existing output states
to be retained. The AND feature of the two Count Enable
inputs (CET•CEP) allows synchronous cascading without
external gating and without delay accumulation over any
practical number of bits or digits.
The Terminal Count (TC) output is HIGH when the Count
Enable Trickle (CET) input is HIGH while the counter is in
its maximum count state (HLLH for the BCD counters,
HHHH for the Binary counters). Note that TC is fully
decoded and will, therefore, be HIGH only for one count
state.
The LS161A and LS163A count modulo 16 following a
binary sequence. They generate a TC when the CET input is
HIGH while the counter is in state 15 (HHHH). From this
state they increment to state 0 (LLLL).
The Master Reset (MR) of the LS161A is asynchronous.
When the MR is LOW, it overrides all other input conditions
and sets the outputs LOW. The MR pin should never be left
open. If not used, the MR pin should be tied through a
resistor to V
CC
, or to a gate output which is permanently set
to a HIGH logic level.
The active LOW Synchronous Reset (SR) input of the
LS163A acts as an edge-triggered control input, overriding
CET, CEP and PE, and resetting the four counter flip-flops
on the LOW to HIGH transition of the clock. This simplifies
the design from race-free logic controlled reset circuits, e.g.,
to reset the counter synchronously after reaching a
predetermined value.
MODE SELECT TABLE
*SR
L
H
H
H
H
PE
X
L
H
H
H
CET
X
X
H
L
X
CEP
X
X
H
X
L
Action on the Rising Clock Edge (
)
RESET (Clear)
LOAD (P
n
→
Q
n
)
COUNT (Increment)
NO CHANGE (Hold)
NO CHANGE (Hold)
*For the LS163A only.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
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3
SN74LS161A, SN74LS163A
LS161A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
V
OL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
−0.65
3.5
0.25
0.35
0.4
0.5
20
40
0.1
0.2
−0.4
−0.8
−20
−100
31
32
Min
2.0
0.8
−1.5
Typ
Max
Unit
V
V
V
V
V
V
μA
mA
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
=
−
18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
I
OL
= 8.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
Output LOW Voltage
Input HIGH Current
MR, Data, CEP, Clock
PE, CET
MR, Data, CEP, Clock
PE, CET
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
I
IH
I
IL
I
OS
I
CC
Input LOW Current
MR, Data, CEP, Clock
PE, CET
Short Circuit Current (Note 2)
Power Supply Current
Total, Output HIGH
Total, Output LOW
mA
mA
mA
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
2. Not more than one output should be shorted at a time, nor for more than 1 second.
LS163A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
V
OL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
−0.65
3.5
0.25
0.35
0.4
0.5
20
40
0.1
0.2
−0.4
−0.8
−20
−100
31
32
Min
2.0
0.8
−1.5
Typ
Max
Unit
V
V
V
V
V
V
μA
mA
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
=
−
18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
I
OL
= 8.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
Output LOW Voltage
Input HIGH Current
Data, CEP, Clock
PE, CET, SR
Data, CEP, Clock
PE, CET, SR
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
I
IH
I
IL
I
OS
I
CC
Input LOW Current
Data, CEP, Clock, PE, SR
CET
Short Circuit Current (Note 3)
Power Supply Current
Total, Output HIGH
Total, Output LOW
mA
mA
mA
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
3. Not more than one output should be shorted at a time, nor for more than 1 second.
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4
SN74LS161A, SN74LS163A
AC CHARACTERISTICS
(T
A
= 25°C)
Limits
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
Parameter
Maximum Clock Frequency
Propagation Delay
Clock to TC
Propagation Delay
Clock to Q
Propagation Delay
CET to TC
MR or SR to Q
Min
25
Typ
32
20
18
13
18
9.0
9.0
20
35
35
24
27
14
14
28
Max
Unit
MHz
ns
ns
ns
ns
V
CC
= 5.0 V
C
L
= 15 pF
Test Conditions
AC SETUP REQUIREMENTS
(T
A
= 25°C)
Limits
Symbol
t
W
CP
t
W
t
s
t
s
t
h
t
h
t
rec
Parameter
Clock Pulse Width Low
MR or SR Pulse Width
Setup Time, other*
Setup Time PE or SR
Hold Time, data
Hold Time, other
Recovery Time MR to CP
Min
25
20
20
25
3
0
15
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
V
CC
= 5.0 V
Test Conditions
*CEP, CET, or DATA
DEFINITION OF TERMS
SETUP TIME (t
s
) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (t
rec
) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
t
W
(H)
CP
1.3 V
t
PHL
Q
1.3 V
t
W
(L)
1.3 V
t
PLH
1.3 V
Other conditions:
PE = MR (SR) = H
CEP = CET = H
MR
1.3 V
t
W
t
rec
Other conditions:
PE = L
P
0
= P
1
= P
2
= P
3
= H
CP
Q
0
V
Q
1
V
Q
2
V
Q
3
1.3 V
t
PHL
1.3 V
Figure 1. Clock to Output Delays, Count
Frequency, and Clock Pulse Width
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
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