CAT871, CAT872
Dual Input Reset Generator
Description
CAT871, CAT872 are dual input reset generators designed to restart
microprocessor and microcontroller based systems when the
watchdog timer or other resetting mechanisms have become disabled
or failed.
CAT871, CAT872 monitor two inputs and output an active low reset
pulse after both inputs have been active (logic low) for a factory preset
minimum time. The reset pulse width is 2.2 ms for CAT871 and 70 ms
for CAT872. Releasing either input from its active state before the
minimum timeout period resets the internal timer and both inputs must
return to being active before the timer will restart with a fresh count
down.
CAT871, CAT872’s open drain output is capable of sinking up to
3 mA of current and may be wire−OR’d with other open drain devices
to drive a common reset input.
Features
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1
ULLGA−6
UL SUFFIX
CASE 613AF
MARKING DIAGRAM
XM
•
•
•
•
•
•
Operate on 1.65 V to 5.5 V Power Supplies
Ultra Low Quiescent Current: 10 nA (typical)
Schmitt Trigger Inputs
8 Factory Preset Delay Times from 0.5 s to 5 s to Choose From
Small
mLLGA−6
Package: 1.45 x 1.0 x 0.4 mm
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Mobile Phones
PDAs
MP3 Players
Personal Navigation Devices
X = Specific Device Code
X =
(J = CAT871, K = CAT872)
M = Date Code
PIN CONNECTIONS
MR1
MR2
NIC
(Top View)
1
VDD
RESET
GND
Typical Applications
•
•
•
•
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Figure 1. Application Schematic
©
Semiconductor Components Industries, LLC, 2011
November, 2011
−
Rev. 0
1
Publication Order Number:
CAT871/D
CAT871, CAT872
FUNCTIONAL BLOCK DIAGRAM
VDD
MR2
Delay Timer
MR1
RESET
Pulse
Generator
RESET
GND
Figure 2. Functional Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
5
6
Pin Name
MR1
MR2
NIC
GND
RESET
VDD
Manual reset input #1. CMOS input.
Manual reset input #2. CMOS input.
No Internal Connection. A voltage or signal applied to this pin will have no effect on device operation.
System Ground.
Reset Output. Active−low open drain output.
Positive Power Supply.
Description
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Input Voltage Range
Output Voltage Range
Input Voltage; MR2, MR1
Maximum Junction Temperature
Output Current; RESET
Storage Temperature Range
ESD Capability, Human Body Model (Note 1)
ESD Capability, Machine Model (Note 1)
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 2)
Symbol
V
DD
V
OUT
V
IN
T
J(max)
I
OUT
T
STG
ESD
HBM
ESD
MM
T
SLD
Value
−0.3
to 6
−0.3
to 6
or (V
DD
+ 0.3), whichever is lower
−0.3
to 6
or (V
DD
+ 0.3), whichever is lower
150
10
−65
to 150
2
200
260
Unit
V
V
V
°C
mA
°C
kV
V
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latch−up Current Maximum Rating:
≤150
mA per JEDEC standard: JESD78
2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
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2
CAT871, CAT872
Table 3. RECOMMENDED OPERATING CONDITIONS
Rating
Input Voltage; VDD
Input Voltage; MR1, MR2
Output Current; RESET
Ambient Temperature
Symbol
V
DD
V
IN
I
OUT
T
A
Min
1.65
0
0
−40
Max
5.5
V
DD
3
85
Unit
V
V
mA
°C
Table 4. ELECTRICAL OPERATING CHARACTERISTICS
Parameter
POWER
V
DD
Supply Voltage
Quiescent Supply Current
Operating Supply Current
MR1 = MR2 = V
DD
.
Test Conditions
(V
DD
= 1.65 V to 5.5 V. For typical values T
A
= 25°C, for min/max values T
A
=
−40°C
to +85°C unless otherwise noted.)
Symbol
Min
Typ
Max
Unit
V
DD
I
DD
MR1 = MR2 = 0 V
Measured during setup period. Measurement
includes current through internal 200 kΩ
pull−up resistor on MR2
1.65
10
5.5
1000
50
V
nA
mA
LOGIC INPUTS AND OUTPUTS
Input Voltage; HIGH
Input Voltage; LOW
Hysteresis
Input Current
Input Current
Output Voltage; HIGH
Output Voltage; LOW
TIMING
Timeout
CAT87x−05
CAT87x−10
CAT87x−15
CAT87x−20
CAT87x−25
CAT87x−30
CAT87x−40
CAT87x−50
Reset Output Pulse Width
CAT871
CAT872
TEST MODE
(at T
A
= 25°C) (Note 3)
Start TEST window
Test Mode delay
Test Mode Clock Frequency
MR2 Test mode clock setup
time
MR2 Input Voltage; LOW
MR2 Pulse Width
3. “Test Mode” parameters are not tested in production.
MR1=0 V, MR2→8 cycles, delay measured
after 8
th
rising edge of the MR2 clock pulse
Clock applied to MR2
Measured from MR1 falling edge to first
falling edge of MR2
MR2, Test mode operation
t
ST
t
D
f
tm
t
P
V
IL_TM
t
pw
500
1
0.2xV
DD
250
1
35
ms
ms
MHz
ms
V
ns
t
R
t
LOW_DELAY
0.41
0.82
1.23
1.64
2.05
2.46
3.28
4.1
1.8
57
0.50
1.00
1.50
2.00
2.50
3.00
4.00
5.00
2.2
70
0.59
1.18
1.77
2.36
2.95
3.54
4.72
5.9
2.6
83
s
s
s
s
s
s
s
s
ms
MR1 = 0 V; V
DD
= 5 V (no internal pull−up)
MR2 = 0 V; V
DD
= 5 V
(internal 200 kW pull−up resistor)
External 10 kW pull−up resistor to V
DD
I
SINK
= 3 mA, V
DD
= 1.8 V
MR1, MR2
MR1, MR2
V
IH
V
IL
V
HYS
I
PU
I
PU
V
OH
V
OL
V
DD
– 0.1
0.1
0.4
−
250
50
25
300
0.7 x V
DD
0.25xV
DD
V
V
mV
nA
mA
V
V
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CAT871, CAT872
TIMING WAVEFORMS
(Note 4)
Figure 3. Timing Waveforms
4. The order of the MR inputs going low does not matter. The last input to go low marks the beginning of t
LOW_DELAY
TYPICAL CHARACTERISTICS
1.75
1.70
1.65
t
LOW_DELAY
(s)
1.55
1.50
1.45
1.40
1.35
1.30
1.25
t
LOW_DELAY
(s)
1.60
−40°C
25°C
90°C
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
−50
5.6 V
3.2 V
1.6 V
1
2
3
VDD (V)
4
5
6
−25
0
25
50
75
100
125 150
TEMPERATURE (°C)
Figure 4. t
LOW_DELAY
vs. VDD (CAT87x−1.5)
Figure 5. t
LOW_DELAY
vs. Temperature
(CAT87x−1.5)
3.5
3.4
3.3
t
LOW_DELAY
(s)
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
−40°C
25°C
90°C
0
1
2
3
VDD (V)
4
5
6
Figure 6. t
LOW_DELAY
vs. VDD (CAT87x−3.0)
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CAT871, CAT872
TYPICAL CHARACTERISTICS
30
25
20
15
85°C
10
25°C
5
0
−40°C
5
0
I
MR2
(mA)
3
VDD (V)
4
5
6
I
DD
(mA)
25
20
15
10
0
1
2
1
2
3
VDD (V)
4
5
6
Figure 7. I
DD
vs. VDD (MR1 = MR2 = 0)
2.6
2.5
2.4
t
R
(ms)
t
R
(ms)
2.3
2.2
2.1
2.0
1.9
1.8
1
2
3
VDD (V)
4
5
6
85°C
−40°C
25°C
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
−50
−25
Figure 8. I
MR2
@ MR2 = 0
5.6 V
3.2 V
1.6 V
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 9. t
R
vs. VDD for CAT871
Figure 10. t
R
vs. Temperature for CAT871
83
81
79
77
75
73
71
69
67
65
63
61
59
57
t
R
(ms)
−40°C
25°C
90°C
0
1
2
3
VDD (V)
4
5
6
Figure 11. Reset Pulse Width for CAT872
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