ESD7102, SZESD7102
ESD Protection Diodes
Low Capacitance ESD Protection Diodes
for High Speed Data Line
The ESD7102 transient voltage suppressor is designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The small form factor,
flow−through style package allows for easy PCB layout and matched
trace lengths necessary to maintain consistent impedance between
high speed differential lines such as USB 3.0 and HDMI.
Features
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MARKING
DIAGRAM
3
2
SC−75
CASE 463
1
E5
M
= Specific Device Code
= Date Code
E5 M
1
•
Low Capacitance (0.3 pF Typical, I/O to GND)
•
Short to Battery Survivability
•
Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4 (ESD)
•
Low ESD Clamping Voltage (34 V Typical, +8 A TLP, I/O to GND)
•
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
PIN CONFIGURATION
AND SCHEMATIC
Pin 1
Pin 2
•
•
•
•
USB2.0/3.0
LVDS
HDMI
High Speed Differential Pairs
Pin 3
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Operating Junction Temperature Range
Storage Temperature Range
Lead Solder Temperature −
Maximum (10 Seconds)
IEC 61000−4−2 Contact
IEC 61000−4−2 Air
ISO 10605 Contact (330 pF / 330
W)
ISO 10605 Contact (330 pF / 2 kW)
ISO 10605 Contact (150 pF / 2 kW)
Symbol
T
J
T
stg
T
L
ESD
Value
−55 to +150
−55 to +150
260
±8
±15
±8
±20
±27
Unit
°C
°C
°C
kV
=
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
©
Semiconductor Components Industries, LLC, 2015
1
October, 2017 − Rev. 1
Publication Order Number:
ESD7102/D
ESD7102, SZESD7102
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (Note 1)
Clamping Voltage TLP (Note 2)
Symbol
V
RWM
V
BR
I
R
V
C
V
C
Conditions
I/O Pin to GND
I
T
= 1 mA, I/O Pin to GND
V
RWM
= 5 V, I/O Pin to GND
IEC61000−4−2,
±8
kV Contact
I
PP
= 8 A
I
PP
= 16 A
I
PP
= −8 A
I
PP
= −16 A
TLP Pulse
V
R
= 0 V, f = 1 MHz between I/O Pins
V
R
= 0 V, f = 1 MHz between I/O Pins and GND
V
R
= 0 V, f = 1 MHz between I/O1 to GND and I/O
2 to GND
f = 1 GHz
f = 3 GHz
f
BW
R
L
= 50
W
34
55
−5.3
−10
1.5
0.2
0.3
5
0.1
0.2
5
0.4
0.5
10
16.5
1
See Figures 1 and 2
V
Min
Typ
Max
16
Unit
V
V
mA
Dynamic Resistance (Note 2)
Junction Capacitance
Junction Capacitance Match
Insertion Loss
3dB Bandwidth
I
R
C
J
DC
J
W
pF
%
dB
GHz
1. For test procedure see Figures 5 and 6 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
= 50
W,
t
p
= 100 ns, t
r
= 4 ns, averaging window; t
1
= 30 ns to t
2
= 60 ns.
120
100
80
VOLTAGE (V)
60
40
20
0
−20
−25
VOLTAGE (V)
25
50
75
100
TIME (ns)
125
150
175
20
0
−20
−40
−60
−80
−100
−120
−25
0
0
25
50
75
100
TIME (ns)
125
150
175
Figure 1. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
1E−02
1E−03
1E−04
1E−05
CURRENT (A)
1E−06
1E−07
1E−08
1E−09
1E−10
1E−11
1E−12
−2
0
2
4
6
8
10
12
14 16 18 20 22 24
CAPACITANCE (pF)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0
Figure 2. IEC61000−4−2 −8 kV Contact ESD
Clamping Voltage
2
4
6
8
10
12
14
16
VOLTAGE (V)
BIAS VOLTAGE (V)
Figure 3. Typical IV Characteristic Curve
Figure 4. Typical CV Characteristic Curve
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2
ESD7102, SZESD7102
IEC 61000−4−2 Spec.
Test Volt-
age (kV)
2
4
6
8
First Peak
Current
(A)
7.5
15
22.5
30
Current at
30 ns (A)
4
8
12
16
Current at
60 ns (A)
2
4
6
8
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
I @ 30 ns
IEC61000−4−2 Waveform
I
peak
100%
90%
Level
1
2
3
4
Figure 5. IEC61000−4−2 Spec
ESD Gun
DUT
Oscilloscope
50
W
Cable
50
W
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
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3
ESD7102, SZESD7102
20
18
16
TLP CURRENT (A)
14
12
10
8
6
4
2
0
0
10
20
30
VOLTAGE (V)
40
50
0
60
2
4
6
8
10
−20
−18
EQUIVALENT V
IEC
(kV)
TLP CURRENT (A)
EQUIVALENT V
IEC
(kV)
−16
−14
6
8
10
−12
−10
−8
−6
−4
−2
0
0
−2
−4
−6
VOLTAGE (V)
−8
−10
4
2
0
−12
Figure 7. Positive TLP IV Curve
Transmission Line Pulse (TLP) Measurement
Figure 8. Negative TLP IV Curve
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 9. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
L
50
W
Coax
Cable
S
Attenuator
÷
10 MW
I
M
50
W
Coax
Cable
V
M
V
C
Oscilloscope
DUT
Figure 9. Simplified Schematic of a Typical TLP
System
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD7102, SZESD7102
Without ESD7102
With ESD7102
Figure 11. USB3.0 Eye Diagram with and without ESD7102 at 5 Gb/s
1
0
−1
CAPACITANCE (pF)
−2
−3
S21 (dB)
−4
−5
−6
−7
−8
−9
−10
1.E+07
1.E+08
1.E+09
FREQUENCY (Hz)
1.E+10
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.0
0.0E+00
1.0E+09
2.0E+09
3.0E+09
V
R
= 0 V
FREQUENCY (Hz)
Figure 12. Typical Insertion Loss
Figure 13. Typical Capacitance over
Frequency
ORDERING INFORMATION
Device
ESD7102BT1G
SZESD7102BT1G*
Package
SC−75
(Pb−Free)
SC−75
(Pb−Free)
Shipping
†
3000 / Tape & Reel
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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5
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