The LV3327PV is electronic volume LSI for the volume adjustment of the portable sound equipment usage.
Features
•
The mixing function is installed, and it is suitable for PND (personal navigation device) as the usage.
It is possible to output it by allocating one system in the audio guidance among four input systems, and mixing other
signals from the speaker output with the audio guidance by the microcomputer control.
•
Because the volume step resolution is 0.5dB step, the volume can be made to fine-tune.
•
The loudness function is installed.
Functions
•
Input switching : 4 input systems (Independent control is possible.)
•
Volumn control : +10dB to -79.5dB(0.5dB steps)/-∞
•
Loudness control :
Taps are output starting at the -32dB position of the ladder resistor and a loudness function implemented with
external capacitor and resistor components.
•
Output gain control : 0dB or +6dB select
•
Mixing function
•
Output switching :
2 outputs (Each Lch output, Rch output, and Lch/Rch mixing output can be selected).
•
Each control is done by the sirial data input. I
2
C
Semiconductor Components Industries, LLC, 2013
June, 2013
42512 SY 20110912-S00004/N2410 SY No.A1879-1/11
LV3327PV
Specifications
Absolute Maximum Ratings
at Ta = 25°C, VSS = 0V
Parameter
Maximum supply voltage
Maximum input voltage
Operating temperature
Storage temperature
Symbol
VDD max
VIN max
Topr
Tstg
VDD
All input pins
Conditions
Ratings
6
VSS-0.3 to VDD
-40 to +85
-50 to +125
Unit
V
V
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ratings
at Ta = 25°C, VSS = 0V
Parameter
Supply voltage
High-level input voltage
Low-level input voltage
Input pulse width
Setup time
Hold time
Operating frequency
Symbol
VDD
VIH
VIL
TφW
Tsetup
Thold
fopg
VDD
DATA, CLK
DATA, CLK
CLK
DATA, CLK
DATA, CLK
CLK
Conditions
Ratings
min
3.0
0.7 VDD
VSS
0.6
0.1
0.9
400
typ
5.0
max
5.5
VDD
0.2 VDD
Unit
V
V
V
μsec
μsec
μsec
kHz
Electrical Characteristics
at Ta = 25°C, VDD = 5V, VSS = 0V
Parameter
A loss of insertion
Input resistance
Volumn step setting error margin
Total harmonic distortion
Maximum attenuation
Output noise voltage
Current drain
Input high-level current
Input low-level current
Maximum input voltage
Symbol
ATT
Rin
ATerr
THD
VO min
VN
IDD
IIH
IIL
VCL
IN1/IN2/IN3/IN4
+10dB to -40dB
VIN = 1Vrms, f = 1kHz
VIN = 1Vrms, f = 1kHz
Rin=1kΩ
DATA, CLK, VIN = 5.0V
DATA, CLK, VIN = 0V
THD = 1% RL = 10kΩ
volumn setting : flat, fIN = 1kHz
-10
1.0
-1.0
0.01
80
5
5
10
Conditions
Ratings
min
-1.0
50
+1.0
typ
max
+1.0
Unit
dB
kΩ
dB
%
dB
μVrms
mA
μA
μA
Vrms
Package Dimensions
unit : mm (typ)
3178B
5.2
16
9
4.4
6.4
1
0.65
(0.33)
8
0.15
0.22
1.5max
SANYO : SSOP16(225mil)
0.1
(1.3)
0.5
No.A1879-2/11
LV3327PV
Pin Assignment
LCT 1
LSELO 2
IN1 3
IN2 4
IN3 5
IN4 6
RSELO 7
RCT 8
TOP VIEW
LV3327PV
16 LOUT
15 TEST
14 VDD
13 DATA
12 CLK
11 VSS
10 VREF
9 ROUT
Block Diagram
LCT
LSELO
Lch MAIN
VOLUME
+10 -79.5dB,-
(0.5dB_step)
Lch
OUTPUT GAIN
0dB,+6dB
LOUT
+
PA
IN2
BIAS
VOLTAGE
CIRCUIT
IN3
LOGIC
DATA
CLK
VSS
LOGIC
RVREF
VREF
I
2
C
INTERFACE
IN4
INMUTE
Rch MAIN
VOLUME
+10 -79.5dB,-
(0.5dB_step)
MUTE
Rch
OUTPUT GAIN
0dB,+6dB
ROUT
PA
RSELO
RCT
No.A1879-3/11
+
+
+
+
+
+
IN1
INMUTE
MUTE
TEST
LVREF
VDD
+
LV3327PV
Pin Functions
Pin
IN1
IN2
IN3
IN4
Pin No.
3
4
5
6
Input pins.
Function
Equivalent Circuit
VDD
LVREF
RVREF
LSELO
RSELO
2
7
Input selector output pins
VDD
+
-
LCT
RCT
1
8
Tap pins for external loudness
VDD
LOUT
ROUT
16
9
Output pins.
VDD
+
-
VREF
10
Connect a capacitor of a few tens of uF between VREF
and AVSS (VSS) as a 0.5
×
VDD voltage generator,
current ripple countermeasure.
VDD
-
+
LVREF
RVREF
CLK
12
Serial data clock input pin for control.
VDD
DATA
13
Serial data input pin for control.
VDD
TEST
VDD
VSS
15
14
11
TEST pin
Normally this pin is OPEN.
Power supply pin.
Ground pin.
No.A1879-4/11
LV3327PV
DATA format : I
2
C data specification
MSB
S
LSB MSB
W A
LSB MSB
A
DATA_1
LSB MSB
A
LSB
AP
CHIP address
SUB address
(Explanation)
S:Start Condition
P:Stop Condition
W:Write 0(Write Mode Only)
A:Ack(Acknowledge)
DATA_N
DATA setting
CHIP address
MSB
LSB
CP7 CP6 CP5 CP4 CP3 CP2 CP1 CP0
W
CP7
1
CP6
0
CP5
0
CP4
0
CP3
0
CP2
0
CP1
1
CP0
0
SUB address
MSB
LSB
SU7 SU6 SU5 SU4 SU3 SU2 SU1 SU0
Block
Input switching control (Lch)
Input switching control (Rch)
Volume control (Lch)
Volume control(Rch)
Loudness
TEST control
Output switching control / Output gain control (Lch)
Output switching control / Output gain control (Rch)
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