NCV7517B
FLEXMOSt Hex Low-Side
MOSFET Pre-Driver
The NCV7517B programmable six channel low−side MOSFET
pre−driver is one of a family of FLEXMOS
TM
automotive grade
products for driving logic−level MOSFETs. The product is
controllable by a combination of serial SPI and parallel inputs. It
features programmable fault management modes and allows
power−limiting PWM operation with programmable refresh time.
The device offers 3.3 V/5.0 V compatible inputs and the serial output
driver can be powered from either 3.3 V or 5.0 V. Power−on reset
provides controlled powerup and two enable inputs allow all outputs
to be simultaneously disabled.
Each channel independently monitors its external MOSFET’s
drain voltage for fault conditions. Shorted load fault detection
thresholds are fully programmable using an externally programmed
reference voltage and a combination of four discrete internal ratio
values. The ratio values are SPI selectable and allow different
detection thresholds for each group of three output channels.
Fault information for each channel is 2−bit encoded by fault type
and is available through SPI communication. Fault recovery
operation for each channel is programmable and may be selected for
latch−off or automatic retry.
The FLEXMOS family of products offers application scalability
through choice of external MOSFETs.
Features
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MARKING
DIAGRAM
LQFP32
FT SUFFIX
CASE 561AB
NCV7517B
AWLYYWWG
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NCV7517BFTG
Package
LQFP
(Pb−Free)
Shipping†
250 Units/Tray
•
•
•
•
•
•
16−Bit SPI with Frame Error Detection
3.3 V/5.0 V Compatible Parallel and Serial Control Inputs
3.3 V/5.0 V Compatible Serial Output Driver
Two Enable Inputs
Open−Drain Fault and Status Flags
Programmable
− Shorted Load Fault Detection Thresholds
− Fault Recovery Mode
− Fault Retry Timer
− Flag Masking
•
Load Diagnostics with Latched Unique Fault Type Data
− Shorted Load
− Open Load
− Short to GND
•
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Benefits
NCV7517BFTR2G
LQFP
2000 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
•
Scalable to Load by Choice of External MOSFET
©
Semiconductor Components Industries, LLC, 2016
1
June, 2016 − Rev. 2
Publication Order Number:
NCV7517B/D
NCV7517B
IN5 IN4 IN3 IN2 IN1 IN0
ENA2
VCC2
NCV7517B
Hex MOSFET Pre−Driver
VCC1
POWER ON RESET
&
POR
BIAS
CHANNEL 0
DRN0
FAULT
DETECT
V
SS
VCC2
ENA1
GATE SELECT
FLAG MASK
DISABLE MODE
REFRESH/REF
ENA ENA VCC2
DRN
1
2
REF
DISABLE
PARALLEL
SERIAL
IREF
ENA ENA VCC2
DRN
1
2
REF
DISABLE
PARALLEL
SERIAL
DRIVER
GAT0
V
SS
CHANNEL 1
DRN1
CSB
VCC
6
VSS
GAT1
DRN2
CHANNEL 2
SCLK
POR
CSB
SCLK
SI
SI
IREF
VSS
GAT2
DRN3
SPI
16 BIT
VDD
ENA ENA VCC2
DRN
1
2
REF
DISABLE
PARALLEL
SERIAL
CHANNEL 3
SO
DRIVER
SO
DRN
ENA ENA VCC2
1
2
REF
DISABLE
PARALLEL
SERIAL
IREF
VSS
GAT3
DRN4
V
SS
CHANNEL 4
12
FAULT BITS
FLTB
FAULT LOGIC
&
REFRESH TIMER
ENA1
ENA ENA VCC2
DRN
1
2
REF
DISABLE
PARALLEL
SERIAL
IREF
VSS
GAT4
DRN5
CHANNEL 5
2
GND
CLOCK
IREF
VSS
GAT5
4
FLTREF
+
FAULT
REFERENCE
GENERATOR
CH
0−2
CH
3−5
DRN 0:5
MASK 0:5
POR
ENA
1
VSS
DRAIN
FEEDBACK
MONITOR
STAB
−
OA
Figure 1. Block Diagram
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2
NCV7517B
28W
28W
14W
M
+5V
POWER−ON
RESET
RX1
CB1
R
FILT
VCC1
FLTREF
ENA1
VCC2
R
D0
+5V OR
+3.3V
DRN0
NID9N05CL
GAT0
R
D1
RST
RX2
ENA2
IN0
IN1
IN2
IN3
DRN1
NID9N05CL
HOST CONTROLLER
PARALLEL
GAT1
R
D2
DRN2
NCV7517B
NID9N05CL
GAT2
R
D3
CB2
NID9N05CL
DRN3
GAT3
R
D4
SPI
IN4
IN5
DRN4
NID9N05CL
IRQ
I/O
FLTB
CSB
SCLK
GAT4
R
D5
DRN5
NID9N05CL
GAT5
VDD
SO
VSS
R
FPU
SI
STAB
R
SPU
GND
Figure 2. Application Diagram
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3
UNCLAMPED LOAD
V
LOAD
14W
5W
NCV7517B
PIN FUNCTION DESCRIPTION
Symbol
FLTREF
DRN0 – DRN5
GAT0 – GAT5
ENA1, ENA2
IN0 – IN5
CSB
SCLK
SI
SO
STAB
FLTB
VCC1
GND
VCC2
VDD
VSS
Description
Analog Fault Detect Threshold: 5.0 V Compliant
Analog Drain Feedback: Internally Clamped
Analog Gate Drive: 5.0 V Compliant
Digital Master Enable Inputs: 3.3 V/5.0 V (TTL) Compatible
Digital Parallel Input: 3.3 V/5.0 V (TTL) Compatible
Digital Chip Select Input: 3.3 V/5.0 V (TTL) Compatible
Digital Shift Clock Input: 3.3 V/5.0 V (TTL) Compatible
Digital Serial Data Input: 3.3 V/5.0 V (TTL) Compatible
Digital Serial Data Output: 3.3 V/5.0 V Compliant
Digital Open−Drain Output: 3.3 V/5.0 V Compliant
Digital Open−Drain Output: 3.3 V/5.0 V Compliant
Power Supply − Low Power Path
Power Return − Low Power Path – Device Substrate
Power Supply − Gate Drivers
Power Supply − Serial Output Driver
Power Return – VCC2, VDD, Drain Clamps
DRN2
DRN3
DRN4
DRN5
GAT2
GAT3
GAT4
24 23 22 21 20 19 18 17
GAT1
DRN1
GAT0
DRN0
VCC2
VCC1
FLTREF
GND
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
16
15
14
VSS
STAB
VDD
SO
SI
SCLK
CSB
FLTB
GAT5
13
12
11
10
9
ENA1
NCV7517B
IN0
IN1
IN2
IN3
IN4
IN5
Figure 3. 32 Pin LQFP Pinout (Top View)
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4
ENA2
NCV7517B
MAXIMUM RATINGS
(Voltages are with respect to device substrate.)
Rating
DC Supply (V
CC1
, V
CC2
, V
DD
)
Difference Between V
CC1
and V
CC2
Difference Between GND (Substrate) and V
SS
Output Voltage (Any Output)
Drain Feedback Clamp Voltage (Note 1)
Drain Feedback Clamp Current (Note 1)
Input Voltage (Any Input)
Junction Temperature, T
J
Storage Temperature, T
STG
Peak Reflow Soldering Temperature: Lead−Free
60 to 150 seconds at 217°C (Note 2)
Value
−0.3 to 6.5
"0.3
"0.3
−0.3 to 6.5
−0.3 to 47
10
−0.3 to 6.5
−40 to 150
−65 to 150
260 peak
Unit
V
V
V
V
V
mA
V
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
ATTRIBUTES
Characteristic
ESD Capability
Human Body Model
Machine Model
Moisture Sensitivity (Note 2)
Package Thermal Resistance (Note 3)
Junction–to–Ambient, R
qJA
Junction–to–Pin, R
YJL
Value
w "
2.0 kV
w "
200 V
MSL2
86.0
°C/W
58.5
°C/W
1. An external series resistor must be connected between the MOSFET drain and the feedback input in the application. Total clamp power
dissipation is limited by the maximum junction temperature, the application environment temperature, and the package thermal resistances.
2. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D, and
Application Note AND8003/D.
3. Values represent still air steady−state thermal performance on a 4 layer (42 x 42 x 1.5 mm) PCB with 1 oz. copper on an FR4 substrate, using
a minimum width signal trace pattern (384 mm
2
trace area).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC1
V
CC2
V
DD
V
IN
High
V
IN
Low
T
A
Main Power Supply Voltage
Gate Drivers Power Supply Voltage
Serial Output Driver Power Supply Voltage
Logic High Input Voltage
Logic Low Input Voltage
Ambient Still−Air Operating Temperature
Parameter
Min
4.75
V
CC1
− 0.3
3.0
2.0
0
−40
Max
5.25
V
CC1
+ 0.3
V
CC1
V
CC1
0.8
125
Unit
V
V
V
V
V
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
Recommended Operating Ranges limits may affect device reliability.
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5
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