NCP6151/NCP6151A
Dual Output 4 Phase +1/0 Phase
Controller with single SVID Interface
for Desktop and Notebook CPU
Applications
The NCP6151/NCP6151A dual output four plus one
phase buck solution is optimized for Intel VR12
compatible CPUs. The controller combines true
differential voltage sensing, differential inductor DCR
current sensing, input voltage feed-forward, and
adaptive voltage positioning to provide accurately
regulated power for both Desktop and Notebook
applications. The control system is based on Dual-Edge
pulse-width modulation (PWM) combined with DCR
current sensing providing the fastest initial response to
dynamic load events and reduced system cost. It also
sheds to single phase during light load operation and
can auto frequency scale in light load while maintaining
excellent transient performance.
Dual high performance operational error amplifiers are
provided to simplify compensation of the system.
Patented Dynamic Reference Injection further simplifies
loop compensation by eliminating the need to
compromise between closed-loop transient response
and Dynamic VID performance. Patented Total Current
Summing provides highly accurate current monitoring for
droop and digital current monitoring.
NCP6151A support coupled inductor operation. It
operates with 2 phases versus NCP6151 operating with
single phase during PS1 mode.
Features
•
Meets Intel VR12/IMVP7 Specifications
•
Current Mode Dual Edge Modulation for Fastest
Initial Response to Transient Loading
•
Dual High Performance Operational Error Amplifier
•
One Digital Soft Start Ramp for Both Rails
•
Dynamic Reference Injection
®
(Patent
#US07057381)
•
Accurate Total Summing Current Amplifier(Patent
#US006683441)
•
DAC with Droop Feed-forward Injection(Patent
Pending)
•
Dual High Impedance Differential Voltage and Total
Current Sense Amplifiers
•
Phase-to-Phase Dynamic Current Balancing
•
“Lossless” DCR Current Sensing for Current
Balancing
•
Summed Thermally Compensated Inductor Current
Sensing for Droop
•
True Differential Current Balancing Sense Amplifiers
for Each Phase
•
Adaptive Voltage Positioning (AVP)
DIF FOUT
VSN
http://onsemi.com
DROOP
CSCOMP
CSSUM
FB
TRBST
CSREF
IOU T
42
43
COMP
52
51
50
49
48
47
46
45
44
VSP
TSENSE
VR_HOT#
SD IO
SC LK
ALERT#
VR_RDY
VR_RDYA
ENABLE
ROSC
VCC
VR MP
TSEN SEA
CSN4
CSP4
40
41
39
ILIM
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
16
17
18
19
20
21
22
23
24
25
26
38
CSN2
CSP2
CSN3
CSP3
CSN1
CSP1
DRVON
PWM1/ADDR
PWM3 /IMAX
PWM2/VBOOT
PWM4
PWMA/IMAXA
VBOOTA
PIN 1
INDIC ATOR
37
36
35
NCP6151
34
33
32
31
Top View
(not to scale)
30
29
28
27
VSNA
DIFFOU TA
F BA
TRBSTA
VSPA
COMPA
ILI MA
DROOPA
CSCOM PA
CSSUMA
IOU TA
QFN52 Dual Row Pin Package
Device
NCP6151D52MNR2G
NCP6151AD52MNR2G
NCP61510091MNR2G
Package
QFN52
Dual Row
QFN52
Dual Row
QFN52
Dual Row
Shipping
CSPA
CSNA
2500/Tape &
Reel
2500/Tape &
Reel
2500/Tape &
Reel
* Pb-free and Halide-free packages are available
•
•
•
•
•
•
•
•
•
Switching Frequency Range of 200KHz –
1.0MHz
Startup into Pre-Charged Loads While
Avoiding False OVP
Power Saving Phase Shedding
Vin Feed Forward Ramp Slope
Pin Programming for Internal SVID
parameters
Over Voltage Protection (OVP) & Under
Voltage Protection (UVP)
Over Current Protection (OCP)
Dual Power Good Output with Internal Delays
NCP6151A support coupled inductor operation
Applications
•
Desktop & Notebook Processors
Rev1, 032012
Page 1
Block Diagram
Rev1, 032012
Page 2
NCP6151 QFN52 Dual Row Pin Diagram
FLAG / GND
(53)
NCP6151/NCP6151A QFN52 Dual Row Pin List and Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Symbol
VSP
TSENSE
VR_HOT#
SDIO
SCLK
ALERT#
VR_RDY
VR_RDYA
ENABLE
ROSC
VCC
VRMP
TSENSEA
Rev1, 032012
Description
Non-inverting input to the core differential remote sense amplifier.
Temp Sense input for the multiphase converter
Thermal logic output for over temperature.
Serial VID data interface.
Serial VID clock.
Serial VID ALERT#.
Open drain output. High indicates that the core output is regulating.
Open drain output. High indicates that the aux output is regulating.
Logic input. Logic high enables both outputs and logic low disables both outputs.
A resistance from this pin to ground programs the oscillator frequency. This pin
supplies a trimmed output voltage of 2V.
Power for the internal control circuits. A decoupling capacitor is connected from this pin
to ground.
Feed-forward input of Vin for the ramp slope compensation. The current fed into this
pin is used to control of the ramp of PWM slope
Temp sense for the single phase converter
Page 3
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
VSPA
VSNA
DIFFOUTA
FBA
TRBSTA
COMPA
ILIMA
DROOPA
CSCOMPA
CSSUMA
IOUTA
CSNA
CSPA
VBOOTA
PWMA/IMAXA
PWM4
PWM2/VBOOT
PWM3/IMAX
PWM1/ADDR
DRON
CSP1
CSN1
CSP3
CSN3
CSP2
CSN2
CSP4
CSN4
IOUT
CSREF
CSSUM
CSCOMP
DROOP
ILIM
COMP
TRBST
FB
DIFFOUT
VSN
FLAG / GND
Non-inverting input to the aux differential remote sense amplifier
Inverting input to the aux differential remote sense amplifier
Output of the aux differential remote sense amplifier
Error amplifier voltage feedback for aux output
Compensation pin for the load transient boost.
Output of the aux error amplifier and the inverting input of the PWM comparator for aux
output
Over current shutdown threshold setting for aux output. A resistor to CSCOMPA sets
the threshold.
Used to program droop function for aux output. It’s connected to the resistor divider
placed between CSCOMPA and CSREFA.
Output of total current sense amplifier for aux output
Inverting input of total current sense amplifier for aux output
Total output current monitor for aux output
Inverting input to aux current sense amplifier
Non-Inverting input to aux current sense amplifier
VBOOTA Voltage input pin. Set to adjust the aux boot-up voltage
Aux PWM output to gate driver. During start up it is used to program ICC_MAXA with a
resistor to ground
Phase 4 PWM output. Pull to VCC to program 3 phase operation.
Phase 2 PWM output. VBoot program pin. During start up it is used to program
VBOOT with a resistor to ground.
Phase 3 PWM output. ICC_MAX Input Pin. During start up it is used to program
ICC_MAX with a resistor to ground.
Phase 1 PWM output. A resistor to ground on this pin programs the SVID address of
the devise.
Bidirectional gate drive enable for core output.
Non-inverting input to current balance sense amplifier for phase 1
Inverting input to current balance sense amplifier for phase 1
Non-inverting input to current balance sense amplifier for phase 3
Inverting input to current balance sense amplifier for phase 3
Non-inverting input to current balance sense amplifier for phase 2
Inverting input to current balance sense amplifier for phase 2
Non-inverting input to current balance sense amplifier for phase 4
Inverting input to current balance sense amplifier for phase 4
Total output current monitor for core output.
Total output current sense amplifier reference voltage input.
Inverting input of total current sense amplifier for core output.
Output of total current sense amplifier for core output.
Used to program droop function for core output. It’s connected to the resistor divider
placed between CSCOMP and CSREF summing node.
Over current shutdown threshold setting for core output. Resistor to CSCOMP to set
threshold.
Output of the error amplifier and the inverting inputs of the PWM comparators for the
core output.
Compensation pin for the load transient boost.
Error amplifier voltage feedback for core output
Output of the core differential remote sense amplifier.
Inverting input to the core differential remote sense amplifier.
Power supply return ( QFN Flag )
Rev1, 032012
Page 4
Four Phase Plus One Phase Application Control Circuit
Rev1, 032012
Page 5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
