NCP6121
Dual Output 3 Phase +1/0
Phase Controller with
Single SVID Interface for
Desktop and Notebook CPU
Applications
The NCP6121 dual output three plus one phase buck solution is
optimized for Intel VR12 compatible CPUs. The controller combines
true differential voltage sensing, differential inductor DCR current
sensing, input voltage feed−forward, and adaptive voltage positioning
to provide accurately regulated power for Desktop applications. The
control system is based on Dual−Edge pulse−width modulation
(PWM) combined with DCR current sensing providing the fastest
initial response to dynamic load events and reduced system cost. It
also sheds to single phase during light load operation and can auto
frequency scale in light load while maintaining excellent transient
performance.
Dual high performance operational error amplifiers are provided to
simplify compensation of the system. Patented Dynamic Reference
Injection further simplifies loop compensation by eliminating the need
to compromise between closed−loop transient response and Dynamic
VID performance. Patented Total Current Summing provides highly
accurate current monitoring for droop and digital current monitoring.
Features
http://onsemi.com
MARKING
DIAGRAM
1 52
QFN−52
CASE 485BE
A
WL
YY
WW
G
NCP6121
AWLYYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 27 of this data sheet.
•
Meets Intel VR12 and IMVP7 Specifications
•
Current Mode Dual Edge Modulation for Fastest Initial Response to
•
•
•
•
•
•
•
•
•
•
•
Transient Loading
Dual High Performance Operational Error Amplifier
One Digital Soft Start Ramp for Both Rails
Dynamic Reference Injection
Accurate Total Summing Current Amplifier
DAC with Droop Feed−forward Injection
Dual High Impedance Differential Voltage and Total
Current Sense Amplifiers
Phase−to−Phase Dynamic Current Balancing
“Lossless” DCR Current Sensing for Current Balancing
Summed Thermally Compensated Inductor Current
Sensing for Droop
True Differential Current Balancing Sense Amplifiers
for Each Phase
Adaptive Voltage Positioning (AVP)
•
Switching Frequency Range of 200 kHz – 1.0 MHz
•
Startup into Pre−Charged Loads While Avoiding False
•
•
•
•
•
•
•
OVP
Power Saving Phase Shedding
Vin Feed Forward Ramp Slope
Pin Programming for Internal SVID parameters
Over Voltage Protection (OVP) and Under Voltage
Protection (UVP)
Over Current Protection (OCP)
Dual Power Good Output with Internal Delays
These Devices are Pb−Free and are RoHS Compliant
Applications
•
Desktop and Notebook Processors
©
Semiconductor Components Industries, LLC, 2011
January, 2011
−
Rev. 1
1
Publication Order Number:
NCP6121/D
NCP6121
BLOCK DIAGRAM FOR NCP6121
Figure 1. Block Diagram
http://onsemi.com
2
NCP6121
NCP6121, QFN52 SINGLE ROW PIN CONFIGURATIONS
CSCOMP
DIFFOUT
DROOP
CSSUM
NC
41
52
51
50
49
48
47
46
45
44
43
42
VSP
TSENSE
VRHOT#
SDIO
SCLK
ALERT#
VR_RDY
VR_RDYA
ENABLE
VCC
ROSC
VRMP
TSENSEA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
FLAG/GND (Pin 53)
40
39
38
37
NC
FB
Pin 1 Indicator
CSREF
TRBST
COMP
IOUT
VSN
ILIM
CSN2
CSP2
CSN3
CSP3
CSN1
CSP1
DRON
PWM1/ADDR
PWM3/VBOOT
PWM2
IMAX
PWMA/IMAXA
VBOOTA
(Not to Scale)
NCP6121
36
35
34
33
32
31
30
29
28
27
DIFFOUTA
TRBSTA
CSCOMPA
CSPA
VSPA
Figure 2. Pinout
(Top View)
NCP6121 QFN52 SINGLE ROW PIN DESCRIPTIONS
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol
VSP
TSENSE
VR_HOT#
SDIO
SCLK
ALERT#
VR_RDY
VR_RDYA
ENABLE
VCC
ROSC
VRMP
TSENSEA
VSNA
VSPA
Description
Non−inverting input to the core differential remote sense amplifier.
Temp Sense input for the multiphase converter
Thermal logic output for over temperature.
Serial VID data interface.
Serial VID clock.
Serial VID ALERT#.
Open drain output. High indicates that the core output is regulating.
Open drain output. High indicates that the aux output is regulating.
Logic input. Logic high enables both outputs and logic low disables both outputs.
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground.
A resistance from this pin to ground programs the oscillator frequency. This pin supplies a trimmed output
voltage of 2 V.
Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used to control
the ramp of PWM slope
Temp Sense input for the single phase converter
Inverting input to the aux differential remote sense amplifier
Non−inverting input to the aux differential remote sense amplifier
http://onsemi.com
3
CSSUMA
DROOPA
COMPA
IOUTA
CSNA
FBA
VSNA
ILIMA
NCP6121
NCP6121 QFN52 SINGLE ROW PIN DESCRIPTIONS
Pin
No.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30*
31
32
33
34
35
36
37
38
39*
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Symbol
FBA
DIFFOUTA
TRBSTA
COMPA
ILIMA
DROOPA
CSCOMPA
IOUTA
CSSUMA
CSPA
CSNA
VBOOTA
PWMA /
IMAXA
IMAX
PWM2
PWM3 /
VBOOT
PWM1 /
ADDR
DRON
CSP1
CSN1
CSP3
CSN3
CSP2
CSN2
NC
NC
CSREF
IOUT
CSSUM
CSCOMP
DROOP
ILIM
COMP
FB
TRBST
VSN
DIFFOUT
FLAG / GND
Error amplifier voltage feedback for aux output
Output of the aux differential remote sense amplifier
Compensation pin for aux rail load transient boost.
Output of the aux error amplifier and the inverting input of the PWM comparator for aux output
Over current shutdown threshold setting for aux output. A resistor to CSCOMPA sets the threshold.
Used to program droop function for aux output. It’s connected to the resistor divider placed between
CSCOMPA and CSREFA.
Output of total current sense amplifier for aux output
Total output current monitor for aux output
Inverting input of total current sense amplifier for aux output
Non−Inverting input to aux current sense amplifier
Inverting input to aux current sense amplifier
VBOOTA Voltage input pin. Set to adjust the aux boot−up voltage
Aux PWM output to gate driver. Also as ICC_MAXA input pin for aux rail. During start up it is used to pro-
gram ICC_MAXA with a resistor to ground
ICC_MAX Input Pin for core rail. During start up it is used to program ICC_MAX with a resistor to ground
Phase 2 PWM output only. Pull to V
CC
will configure as 2−phase operation.
Phase 3 PWM output. Also as VBOOT input pin to adjust the core rail boot−up voltage. During start up it is
used to program VBOOT with a resistor to ground.
Phase 1 PWM output. Also as Address program pin. A resistor to ground on this pin programs the SVID
address of the device.
Bidirectional gate drive enable for core output.
Non−inverting input to current balance sense amplifier for phase 1
Inverting input to current balance sense amplifier for phase 1
Non−inverting input to current balance sense amplifier for phase 3
Inverting input to current balance sense amplifier for phase 3
Non−inverting input to current balance sense amplifier for phase 2
Inverting input to current balance sense amplifier for phase 2
No connection
No connection
Total output current sense amplifier reference voltage input.
Total output current monitor for core output.
Inverting input of total current sense amplifier for core output.
Output of total current sense amplifier for core output.
Used to program droop function for core output. It’s connected to the resistor divider placed between
CSCOMP and CSREF summing node.
Over current shutdown threshold setting for core output. Resistor to CSCOMP to set threshold.
Output of the error amplifier and the inverting inputs of the PWM comparators for the core output.
Error amplifier voltage feedback for core output
Compensation pin for core rail load transient boost.
Inverting input to the core differential remote sense amplifier.
Output of the core differential remote sense amplifier.
Power supply return (QFN Flag)
Description
http://onsemi.com
4
NCP6121
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol
COMP,COMPA
CSCOMP, CSCOMPA
VSN
DIFFOUT, DIFFOUTA
VR_RDY,VR_RDYA
VCC
ROSC
IOUT, IOUTA Output
VRMP
All Other Pins
**All signals referenced to GND unless noted otherwise.
V
MAX
VCC + 0.3 V
VCC + 0.3 V
GND + 300 mV
VCC + 0.3 V
VCC + 0.3 V
6.5 V
VCC + 0.3 V
2.0 V
+25 V
VCC + 0.3V
V
MIN
−0.3
V
−0.3
V
GND – 300 mV
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
Unit
V
V
mV
V
V
V
V
V
V
V
THERMAL INFORMATION
Pin Symbol
Thermal Characteristic
QFN Package, (Note 1)
Operating Junction Temperature Range, (Note 2)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Moisture Sensitivity Level
QFN Package
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
T
STG
MSL
Symbol
R
qJA
T
J
Typ
68
−10
to 125
−10
to 100
−
40 to +150
1
Unit
°C/W
°C
°C
°C
NCP6121 ELECTRICAL CHARACTERISTICS
Unless otherwise stated:
−10°C
< T
A
< 100°C; V
CC
= 5 V; C
VCC
= 0.1
mF
Parameter
ERROR AMPLIFIER
Input Bias Current
Open Loop DC Gain
Open Loop Unity Gain Bandwidth
Slew Rate
@ 1.3 V
C
L
= 20 pF to GND,
R
L
= 10 kW to GND
C
L
= 20 pF to GND,
R
L
= 10 kW to GND
DV
in
= 100 mV, G =
−10
V/V,
DV
out
= 1.5 V – 2.5 V,
C
L
= 20 pF to GND, DC Load =
10k to GND
I
SOURCE
= 2.0 mA
I
SINK
= 2.0 mA
VSP, VSPA ,VSN, VSNA = 1.3 V
3.5
−
−400
80
55
20
400
nA
dB
MHz
V/ms
Test Conditions
Min
Typ
Max
Unit
Maximum Output Voltage
Minimum Output Voltage
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current
VSP Input Voltage Range
VSN Input Voltage Range
−
−
−
1
V
V
−400
−0.3
−0.3
−
−
−
400
3.0
0.3
nA
V
V
http://onsemi.com
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
