NCP5424A
Dual Synchronous
Buck Controller with Input
Current Sharing
The NCP5424A is a flexible dual N−channel synchronous buck
controller utilizing V
2
™
control for fast transient response and
excellent line and load regulation. This highly versatile controller can
be configured as a single two phase output converter that draws
programmable amounts of current from two different input voltages or
all current from one supply. The NCP5424A can also be configured as
two independent out−of−phase controllers.
Using the NCP5424A in a current sharing input configuration is
ideal for applications where more power is required than is available
from one supply, such as video cards or other plug−in boards. When
configured as a dual output controller, the output of one controller can
be divided down and used as the reference for the second controller.
This tracking capability is useful in applications such as Double Data
Rate (DDR) Memory power where the termination voltage must track
VDD.
The NCP5424A provides a cycle−to−cycle current limit allowing
the system to handle transient overcurrent events. In addition, the
NCP5424A provides Soft Start, undervoltage lockout, and built−in
adaptive FET nonoverlap time to prevent shoot through.
Features
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SO−16
D SUFFIX
CASE 751B
1
16
PIN CONNECTIONS AND
MARKING DIAGRAM
1
GATE(H)1
GATE(L)1
GND
BST
IS+1
IS−
V
FB1
COMP1
16
GATE(H)2
GATE(L)2
V
CC
R
OSC
IS+2
V
FB+2
V
FB−2
COMP2
NCP5424A
AWLYWW
•
•
•
•
•
•
Cycle−to−Cycle Current Limit
Programmable Soft Start
100% Duty Cycle for Enhanced Transient Response
150 kHz to 600 kHz Programmable Frequency Operation
Switching Frequency Set by Single Resistor
Out−Of−Phase Synchronization Between the Channels Reduces the
Input Filter Requirement
•
Undervoltage Lockout
Applications
A
WL
Y
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
NCP5424AD
NCP5424ADR2
Package
SO−16
SO−16
Shipping
48 Units/Rail
2500 Tape & Reel
•
•
•
•
Video Graphics Card
DDR Memory
High Current (Two−Phase) Power Supplies
Dual Output DC−DC Converters
©
Semiconductor Components Industries, LLC, 2003
1
August, 2003 − Rev. 0
Publication Order Number:
NCP5424A/D
NCP5424A
12 V
3.3 V
5.0 V
+
+
C17
+
C18
220
µF
C2
220
µF
+
220
µF
C1
220
µF
C6
C11
0.1
µF
R1
xk
R2
xk
L2
+
C3/4/5
1.0
µF
U1
V
CC
Q3
MTD60N03
Q4
MTD90N02
IS+1
IS+2
NCP5424A
IS−
COMP1
R5
5 k
±
1%
C8
.22
µF
V
FB1
GND
V
FB−2
R
OSC
R12
30.9 k
V
FB+2
COMP2
C13
0.01
µF
C14
0.1
µF
GATE(L)1
GATE(L)2
Q2
MTD90N02
R17
4k
GATE(H)1
BST
GATE(H)2
Q1 MTD60N03
L1
1.3
µH/15
A
+
1.3
µH/15
A
680
µF/
4V
C19/20/21
680
µF/
4V
R3
x k
±
1%
R4
x k
±
1%
R6
10 k
±
1%
1.5 V @ 20 A
Figure 1. Two−Phase Buck Regulator Application, with Input Current Sharing
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2
NCP5424A
MAXIMUM RATINGS*
Rating
Operating Junction Temperature, T
J
Storage Temperature Range, T
S
ESD Susceptibility (Human Body Model)
Package Thermal Resistance, SO−16:
Lead Temperature Soldering:
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
Junction−to−Case, R
θJC
Junction−to−Ambient, R
θJA
Reflow: (SMD styles only) (Note 1)
Value
150
−65 to +150
2.0
28
115
230 peak
Unit
°C
°C
kV
°C/W
°C/W
°C
MAXIMUM RATINGS
Pin Symbol
V
CC
COMP1, COMP2
V
FB1
, V
FB+2
, V
FB−2
BST
R
OSC
GATE(H)1
,
GATE(H)2
GATE(L)1
,
GATE(L)2
GND
IS+1, IS+2
IS−
Pin Name
IC Power Input
Compensation Capacitor for
Channel 1 or 2
Voltage Feedback Input for
Channel 1 or 2
Power Input for GATE(H)1, 2
Oscillator Resistor
High−Side FET Driver
for Channel 1 or 2
Low−Side FET Driver for
Channel 1 or 2
Ground
Positive Current Sense for
Channel 1 or 2
Negative Current Sense for
Channels 1 and 2
V
MAX
16 V
4.0 V
5.0 V
20 V
4.0 V
20 V
16 V
0V
6.0 V
6.0 V
V
MIN
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
0V
−0.3 V
−0.3 V
I
SOURCE
N/A
1.0 mA
1.0 mA
N/A
1.0 mA
1.5 A peak
200 mA DC
1.5 A peak
200 mA DC
1.5 A peak
200 mA DC
1.0 mA
1.0 mA
I
SINK
1.5 A peak
200 mA DC
3.5 mA
1.0 mA
1.5 A peak
200 mA DC
1.0 mA
1.5 A peak
200 mA DC
1.5 A peak
200 mA DC
N/A
1.0 mA
1.0 mA
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NCP5424A
ELECTRICAL CHARACTERISTICS
(0°C < T
A
< 70°C; 0°C < T
J
< 125°C; R
OSC
= 30.9 k, C
COMP1,2
= 0.1
µF,
10.8 V < V
CC
< 13.2 V; 10.8 V < BST < 20 V, C
GATE(H)1,2
= C
GATE(L)1,2
= 1.0 nF, V
FB+2
= 1.0 V; unless otherwise specified.)
Characteristic
Error Amplifier
V
FB
Bias Current
V
FB1(2)
Input Range
COMP1,2 Source Current
COMP1,2 Sink Current
Reference Voltage 1(2)
COMP1,2 Max Voltage
COMP1,2 Min Voltage
Open Loop Gain
Unity Gain Band Width
PSRR @ 1.0 kHz
Transconductance
Output Impedance
Input Offset, Error Amp. 2
Error Amp. 2 Common Mode Range
GATE(H) and GATE(L)
High Voltage (AC)
Low Voltage (AC)
Rise Time
Measure: V
CC
− GATE(L)1,2;
BST − GATE(H)1,2; Note 2
Measure:GATE(L)1,2 or GATE(H)1,2; Note 2
1.0 V < GATE(L)1,2 < V
CC
− 1.0 V
1.0 V < GATE(H)1,2 < BST − 1.0 V,
BST
≤
14 V
V
CC
− 1.0 > GATE(L)1,2 > 1.0 V
BST − 1.0 > GATE(H)1,2 > 1.0 V,
BST
≤
14 V
GATE(H)1,2 < 2.0 V, GATE(L)1,2 > 2.0 V
BST
≤
14 V
GATE(L)1,2 < 2.0 V, GATE(H)1,2 > 2.0 V;
BST
≤
14 V
Resistance to GND
Note 2
−
−
−
0
0
20
0.5
0.5
50
V
V
ns
Note 2
V
FBX
= 0 V
Note 2
COMP1,2 = 1.2 V to 2.5 V; V
FB1(−2)
= 0.8 V
COMP1,2 = 1.2 V; V
FB1(−2)
= 1.2 V
COMP1 = V
FB1
; COMP2 = V
FB−2
V
FB1(−2)
= 0.8 V
V
FB1(−2)
= 1.2 V
−
−
−
−
−
−
−
0
15
15
0.980
3.0
−
−
−
−
−
−
−3.0
1.75
0.5
−
30
30
1.000
3.3
0.25
95
40
70
32
2.5
0
2.0
1.6
1.1
60
60
1.020
−
0.35
−
−
−
−
−
3.0
−
µA
V
µA
µA
V
V
V
dB
kHz
dB
mmho
MΩ
mV
V
Test Conditions
Min
Typ
Max
Unit
Fall Time
−
15
50
ns
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE(H)1(2) and GATE(L)1(2) pull−down.
PWM Comparator
PWM Comparator Offset
Artificial Ramp
Minimum Pulse Width
20
20
50
40
40
125
70
70
280
ns
ns
kΩ
V
FB1(−2)
= 0 V; Increase COMP1,2 until
GATE(H)1,2 starts switching
Duty cycle = 50%, Note 2
Note 2
0.30
60
−
0.40
105
−
0.50
150
300
V
mV
ns
2. Guaranteed by design, not 100% tested in production.
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NCP5424A
ELECTRICAL CHARACTERISTICS (continued)
(0°C < T
A
< 70°C; 0°C < T
J
< 125°C; R
OSC
= 30.9 k, C
COMP1,2
= 0.1
µF,
10.8 V < V
CC
< 13.2 V; 10.8 V < BST < 20 V, C
GATE(H)1,2
= C
GATE(L)1,2
= 1.0 nF, V
FB+2
= 1.0 V; unless otherwise specified.)
Characteristic
Oscillator
Switching Frequency
Switching Frequency
Switching Frequency
R
OSC
Voltage
Phase Difference
Supply Currents
V
CC
Current
BST Current
Undervoltage Lockout
Start Threshold
Stop Threshold
Hysteresis
Cycle−to−Cycle Current Limit
OVC Comparator Offset Voltage
IS+ 1, 2 Bias Current
OVC Common Mode Range
OVC Latch COMP2 Discharge Current
Discharge Threshold
IS− Bias Current
OVC Latch COMP1 Discharge Current
0 V < IS− < 5.5 V
COMP1 = 1.0 V
COMP = 1.0 V
−
0 V < IS+ 1, 2 < 5.5 V, 0 V < IS− < 5.5 V
0 V < IS+ 1, 2 < 5.5 V
−
55
−1.0
0
0.3
0.20
−2.0
2.0
70
0.1
−
1.2
0.25
0.2
5.0
85
1.0
5.5
3.5
0.30
2.0
8.0
mV
µA
V
mA
V
µA
µA
GATE(H) Switching; COMP1,2 charging
GATE(H) not switching; COMP1,2 discharging
Start−Stop
7.8
7.0
0.5
8.6
7.8
0.8
9.4
8.6
1.5
V
V
V
COMP1,2 = 0 V (No Switching)
COMP1,2 = 0 V (No Switching)
−
−
13
3.5
17
6.0
mA
mA
R
OSC
= 61.9 k; Measure GATE(H)1; Note 3
R
OSC
= 30.9 k; Measure GATE(H)1
R
OSC
= 15.1 k; Measure GATE(H)1; Note 3
R
OSC
= 30.9 k, Note 3
−
112
250
450
0.970
−
150
300
600
1.000
180
188
350
750
1.030
−
kHz
kHz
kHz
V
°
Test Conditions
Min
Typ
Max
Unit
3. Guaranteed by design, not 100% tested in production.
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