NCP5162
General Purpose
Synchronous Buck Controller
The NCP5162 is a synchronous dual N−Channel buck controller
designed to provide unprecedented transient response for today’s
demanding high−density, high−speed logic. It operates using a
proprietary control method which allows a 100 ns response time to
load transients. The NCP5162 is designed to operate over a 9−16 V
range (V
CC
) using 12 V to power the IC and 5.0 V as the main supply
for conversion.
The NCP5162 is specifically designed for high performance core
logic. It includes the following features: 0.8% output tolerance, V
CC
monitor, and programmable Soft Start capability. The NCP5162 is
available in a 16 pin surface mount package.
Features
•
Dual N−Channel Design
•
Excess of 1.0 MHz Operation
•
100 ns Transient Response
•
2.0 A Gate Drivers
•
1.02 V Reference Voltage with 0.8% Tolerance
•
5.0 V & 12 V Operation
•
Remote Sense
•
Programmable Soft Start
•
Lossless Short Circuit Protection
•
V
CC
Monitor
•
V
2
™
Control Topology
•
Overvoltage Protection
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MARKING
DIAGRAM
16
SO−16
D SUFFIX
CASE 751B
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
NCP5162
AWLYWW
PIN CONNECTIONS
Disable
NC
NC
NC
SS
NC
C
OFF
V
FFB
1
16
V
FB
COMP
LGND
V
CC1
V
GATE(L)
PGND
V
GATE(H)
V
CC2
ORDERING INFORMATION
Device
NCP5162D
NCP5162DR2
Package
SO−16
SO−16
Shipping
48 Units/Rail
2500 Tape & Reel
©
Semiconductor Components Industries, LLC, 2006
July, 2006
−
Rev. 4
1
Publication Order Number:
NCP5162/D
NCP5162
12 V
5.0 V
1.0
μH
100 pF
1200
μF/10
V
×
3
Sanyo GX
V
CC1
V
CC2
V
GATE(H)
IRF7413
IRF7413
Disable
NCP5162
C
OFF
270 pF
PGND
SS
0.1
μF
V
FB
COMP
V
FFB
LGND
0.1
μF
100 pF
1.33 k
2.0 k
3.3 k
V
GATE(L)
IRF7413
1.6
μH
IRF7413
V
OUT
1200
μF/10
V
×
3
Sanyo GX
Figure 1. Application Diagram, 5.0 V to 2.5 V/20 A Core Logic Converter with 12 V Bias
MAXIMUM RATINGS*
Rating
Operating Junction Temperature, T
J
Storage Temperature Range, T
S
ESD Susceptibility (Human Body Model)
Thermal Resistance, Junction−to−Case, R
ΘJC
Thermal Resistance, Junction−to−Ambient, R
ΘJA
Lead Temperature Soldering:
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
Reflow: (Note 1)
Value
0 to 150
−65
to +150
2.0
28
115
230 peak
Unit
°C
°C
kV
°C/W
°C/W
°C
MAXIMUM RATINGS
Pin Name
V
CC1
V
CC2
SS
COMP
V
FB
C
OFF
V
FFB
Disable
Max Operating Voltage
16 V/−0.3 V
18 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
Max Current
100 mA DC/3.0 A peak
100 mA DC/3.0 A peak
−100
μA
200
μA
−0.2
μA
−0.2
μA
−0.2
μA
−50
μA
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2
NCP5162
MAXIMUM RATINGS (continued)
Pin Name
V
GATE(H)
V
GATE(L)
LGND
PGND
Max Operating Voltage
18 V/−0.3 V
16 V/−0.3 V
0V
0V
Max Current
100 mA DC/3.0 A peak
100 mA DC/3.0 A peak
25 mA
100 mA DC/3.0 A peak
ELECTRICAL CHARACTERISTICS
(0°C < T
A
< +70°C; 0°C < T
J
< +125°C; 9.5 V < V
CC1
< 14 V; 5.0 V < V
CC2
< 16 V;
CV
GATE(L)
and CV
GATE(H)
= 6.6 nF; C
OFF
= 330 pF; C
SS
= 0.1
μF,
unless otherwise specified.)
Characteristic
Error Amplifier
Reference Voltage
V
FB
Bias Current
Open Loop Gain
Unity Gain Bandwidth
COMP SINK Current
COMP SOURCE Current
COMP CLAMP Current
COMP High Voltage
COMP Low Voltage
PSRR
Transconductance
V
CC1
Monitor
Start Threshold
Stop Threshold
Hysteresis
Soft Start (SS)
Charge Time
Pulse Period
Duty Cycle
COMP Clamp Voltage
V
FFB
SS Fault Disable
High Threshold
PWM Comparator
Transient Response
V
FFB
Bias Current
V
FFB
= 0 to 5.0 V to V
GATE(H)
= 9.0 V to 1.0 V;
V
CC1
= V
CC2
= 12 V
V
FFB
= 0 V
−
−
100
0.3
125
−
ns
μA
−
−
(Charge Time /Pulse Period)
×
100
V
FB
= 0 V; V
SS
= 0
V
GATE(H)
= Low; V
GATE(L)
= Low
−
1.6
25
1.0
0.50
0.9
−
3.3
100
3.3
0.95
1.0
2.5
5.0
200
6.0
1.10
1.1
3.0
ms
ms
%
V
V
V
Output switching
Output not switching
Start−Stop
8.60
8.45
−
8.95
8.80
150
9.30
9.15
−
V
V
mV
Measure V
FB
= COMP
V
FB
= 0 V
1.25 V < V
COMP
, 4.0 V; C
COMP
= 0.1
μF;
Note 2
C
COMP
= 0.1
μF;
Note 2
V
COMP
= 1.5 V; V
FB
= 3.0 V; V
SS
> 2.0 V
V
COMP
= 1.2 V; V
FB
= 2.7 V; V
SS
= 5.0 V
V
COMP
= 0 V; V
FB
= 2.7 V
V
FB
= 2.7 V; V
SS
= 5.0 V
V
FB
= 3.0 V
8.0 V < V
CC1
< 14 V @ 1.0 kHz;
C
COMP
= 0.1
μF;
Note 2
−
1.012
−
−
−
30
15
0.4
4.0
−
−
−
1.02
0.3
80
50
60
30
1.0
4.3
1.00
70
33
1.028
1.0
−
−
120
60
1.6
5.0
1.15
−
−
V
μA
dB
kHz
μA
μA
mA
V
V
dB
mmho
Test Conditions
Min
Typ
Max
Unit
2. Guaranteed by design, not 100% tested in production.
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3
NCP5162
ELECTRICAL CHARACTERISTICS (continued)
(0°C < T
A
< +70°C; 0°C < T
J
< +125°C; 9.5 V < V
CC1
< 14 V; 5.0 V < V
CC2
< 16 V;
CV
GATE(L)
and CV
GATE(H)
= 6.6 nF; C
OFF
= 330 pF; C
SS
= 0.1
μF,
unless otherwise specified.)
Characteristic
Disable Input
Threshold Voltage
Pull Down Resistance
Pull Down Voltage
V
GATE(H)
and V
GATE(L)
Out Rise Time
Out Fall Time
Delay V
GATE(H)
to V
GATE(L)
Delay V
GATE(L)
to V
GATE(H)
V
GATE(H),
V
GATE(L)
Resistance
V
GATE(H),
V
GATE(L)
Schottky
Supply Current
I
CC1
No Switching
I
CC2
No Switching
Operating I
CC1
Operating I
CC2
C
OFF
Charge Time
Discharge Current
Time Out Timer
Time Out Time
Fault Mode Duty Cycle
V
FB
= V
COMP
; V
FFB
= 2.0 V;
Record V
GATE(H)
Pulse High Duration
V
FFB
= 0V
10
35
30
50
65
70
μs
%
V
FFB
= 1.5 V; V
SS
= 5.0 V
C
OFF
to 5.0 V; V
FB
> 1.0 V
1.0
5.0
1.6
−
2.2
−
μs
mA
V
FB
= COMP = V
FFB
V
FB
= COMP = V
FFB
−
−
−
−
−
−
14
11
14
11
17.5
13
17
13.5
mA
mA
mA
mA
1.0 V < V
GATE(H)
< 9.0 V; 1.0 V < V
GATE(L)
< 9.0 V; V
CC1
= V
CC2
= 12 V
9.0 V < V
GATE(H)
> 1.0 V; 9.0 V > V
GATE(L)
> 1.0 V; V
CC1
= V
CC2
= 12 V
V
GATE(H)
falling to 1.0 V
;
V
CC1
= V
CC2
= 8.0 V
CV
GATE(H)
= 6.6 nF; V
GATE(L)
rising to 1.0 V
V
GATE(L)
falling to 1.0 V; V
CC1
= V
CC2
= 8.0 V
CV
GATE(H)
= 6.6 nF; V
GATE(H)
rising to 1.0 V
Resistor to LGND. Note 3
LGND to V
GATE(H)
@ 10 mA;
LGND to V
GATE(L)
@ 10 mA
−
−
45
45
20
−
30
30
70
70
50
600
50
50
95
95
100
800
ns
ns
ns
ns
kΩ
mV
−
−
−
1.00
25
0.00
1.25
50
0.00
2.40
110
0.15
V
kΩ
V
Test Conditions
Min
Typ
Max
Unit
3. Guaranteed by design, not 100% tested in production.
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4
NCP5162
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO−16
1
Disable
This pin is internally pulled down to ground through a resistor,
providing a logic 0 if left open. When pulled to V
CC
, The output gate
drivers are pulled low, powering off the external output stage. At the
same time the Soft Start capacitor is slowly discharged by an internal
2.0
μA
current source, setting the time out before the IC is restarted.
No connection.
Soft Start Pin. A capacitor from this pin to LGND in conjunction with
internal 60
μA
current source provides Soft Start function for the
controller. This pin disables fault detect function during Soft Start.
When a fault is detected, the Soft Start capacitor is slowly discharged
by internal 2.0
μA
current source setting the time out before trying to
restart the IC. Charge/discharge current ratio of 30 sets the duty cycle
for the IC when the regulator output is shorted.
A capacitor from this pin to ground sets the time duration for the on
board one shot, which is used for the constant off time architecture.
Fast feedback connection to the PWM comparator. This pin is
connected to the regulator output. The inner feedback loop
terminates on time.
Boosted power for the high side gate driver.
High FET driver pin capable of 3.0 A peak switching current. Internal
circuit prevents V
GATE(H)
and V
GATE(L)
from being in high state
simultaneously.
High current ground for the IC. The MOSFET drivers are referenced
to this pin. Input capacitor ground and the source of lower FET should
be tied to this pin.
Low FET driver pin capable of 3.0 A peak switching current.
Input power for the IC and low side gate driver.
Signal ground for the IC. All control circuits are referenced to this pin.
Error amplifier compensation pin. A capacitor to ground should be
provided externally to compensate the amplifier.
Error amplifier DC feedback input. This is the master voltage
feedback which sets the output voltage. This pin can be connected
directly to the output or a remote sense trace.
PIN SYMBOL
FUNCTION
2, 3, 4, 6
5
NC
SS
7
8
C
OFF
V
FFB
9
10
V
CC2
V
GATE(H)
11
PGND
12
13
14
15
16
V
GATE(L)
V
CC1
LGND
COMP
V
FB
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