NCP3232N
High Current Synchronous
Buck Converter
The NCP3232N is a high current, high efficiency voltage−mode
synchronous buck converter which operates from 4.5 V to 21 V input
and generates output voltages down to 0.6 V at up to 15 A.
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Features
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Wide Input Voltage Range from 4.5 V to 21 V
0.6 V Internal Reference Voltage
500 kHz Switching Frequency
External Programmable Soft−Start
Lossless Low−side FET Current Sensing
Output Over−voltage Protection and Under−voltage Protection
System Over−temperature Protection using a Thermistor or Sensor
Hiccup Mode Operation for all Faults
Pre−bias Start−up
Adjustable Output Voltage
Power Good Output
Internal Over−temperature Protection
These Devices are Pb−Free and are RoHS Compliant*
MARKING
DIAGRAM
1
1 40
QFN40 6x6, 0.5P
CASE 485CM
NCP3232N
AWLYYWWG
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
COMP
AGND
ISET
OTS
VIN
VIN
VIN
PG
SS
FB
Typical Application
Cellular Base Stations
ASIC, FPGA, DSP and CPU Core and I/O Supplies
Telecom and Network Equipment
Server and Storage System
10
9
8
7
6
5
4
3
2
1
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
11
12
13
14
15
16
17
18
19
20
24
25
29
VSWH
30
40
EN
VIN
EP42
GND
EP41
39
VCC
38
VB
37
PGND
36
BST
35
VSW
VSWH
EP43
34
VSWH
33
VSWH
32
VSWH
31
VSWH
21
22
23
26
27
28
PGND
(TOP VIEW)
ORDERING INFORMATION
Device
NCP3232NMNTXG
Package
QFN−40
(Pb−Free)
Shipping
†
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2015
1
August, 2017 − Rev. 7
Publication Order Number:
NCP3232N/D
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
NCP3232N
VB
VCC
LDO
VB
VCC
VB
VB
BST
OSC
COMP
VREF
VB
+
E/A
−
VIN
FB
Control Logic
Ramp Generator
PWM Logic
− and −
VSWH
SS
Soft Start
VCC
2
mA
VB
Enable
Logic
UVLO
OVP, UVP
Power Good
OCP, TSD
Protection
VSW
VB
EN
1.2 V
POR
PG
VB
+
−
VREF
PGND
OTS
AGND
ISET
Figure 1. NCP3232N Block Diagram
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2
NCP3232N
PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8−14, EP42
15, 29−34,
EP43
16−28, 37
35
36
38
39
40
Symbol
SS
FB
COMP
ISET
AGND
OTS
PG
VIN
VSWH
Description
A capacitor from this pin to GND allows the user to adjust the soft−start ramp time.
Output voltage feedback.
Output of the error amplifier.
A resistor from this pin to ground sets the over−current protection (OCP) threshold.
Analog ground.
Negative input of internal thermal comparator. Tie this pin to ground if not in use.
Power good indicator of the output voltage. Open−drain output. Connect PG to VDD with an extern-
al resistor.
The VIN pin is connected to the internal power NMOS switch. The VIN pin has high di/dt edges and
must be decoupled to ground close to the pin of the device.
The VSWH pin is the connection of the drain and source of the internal NMOS switches. At switch
off, the inductor will drive this pin below ground as the body diode and the NMOS conducts with a
high dv/dt.
Ground reference and high−current return path for the bottom gate driver and low- side NMOS
IC connection to the switch node between the top MOSFET and bottom MOSFET. Return path of
the high−side gate driver.
Top gate driver input supply, a bootstrap capacitor connection between SWN and this pin.
The internal LDO output and input supply for the charge pump. Connect a minimum of 4.7uF ce-
ramic capacitor from this pin to ground.
Input Supply for IC. This pin must be connected to VIN.
Logic control for enabling the switcher. An internal pull−up enables the device automatically. The
EN pin can also be driven high to turn on the device, or low to turn off the device. A comparator
and precision reference allow the user to implement this pin as an adjustable UVLO circuit.
Exposed Pad. Connect GND to a large copper plane at ground potential to improve thermal dissip-
ation.
PGND
VSW
BST
VB
VCC
EN
EP41
GND
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NCP3232N
VIN
VIN
VCC
VSWH
VSW
VB
PGND
BST
VOUT
NCP3232N
ISET
AGND
VPG
EN
OTS
PG
SS
COMP
FB
1 MW
Figure 2. Typical Application Circuit
ABSOLUTE MAXIMUM RATINGS
(measured vs. GND pad, unless otherwise noted)
Rating
Power Supply to GND
VSW to GND
Symbol
V
IN
, V
CC
VSWH, VSW
Value
23
−0.3
30
−0.6 (DC)
35 (t < 50 ns)
−5 (t < 100 ns)
35 (DC)
−0.6 (DC)
40 (t < 50 ns)
6.5(DC)
−0.3(DC)
6.0
−0.3
T
A
T
J
T
J(MAX)
T
stg
HBM
CDM
−40 to +85
−40 to +125
+150
−55 to +150
1.0
2.0
Unit
V
V
BST to GND
BST
V
BST to VSW
All other pins
Operating Ambient Temperature Range
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Electrostatic Discharge − Human Body Model
Electrostatic Discharge − Charge Device Model
V
V
°C
°C
°C
°C
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL INFORMATION
Rating
HS FET Junction−to−case thermal resistance (Note 1)
LS FET Junction−to−case thermal resistance (Note 1)
Junction−to−ambient thermal resistance
Symbol
R
qJC−HS
R
qJC−LS
R
qJA
Value
1.3
0.6
35
Unit
°C/W
°C/W
°C/W
1. R
θJC
thermal resistance is obtained by simulating a cold plate test on the exposed power pad. No specific JEDEC standard test exists, but
a close description can be found in the ANSI SEMI standard G30−88.
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4
NCP3232N
ELECTRICAL CHARACTERISTICS
(−40°C < T
J
< +125°C, V
CC
= 12 V, for min/max values unless otherwise noted, T
J
= +25°C
for typical values)
Parameter
POWER SUPPLY
VIN/VCC Operation Voltage
VB UVLO Threshold (Rising)
VB UVLO Threshold (Falling)
VB Output Voltage
VB Dropout Voltage
VCC Quiescent Current
Shutdown Supply Current
VB
VCC = 6 V, 0
≤
IB
≤
40 mA
IB = 25 mA, VCC = 4.5 V
EN = H, COMP = H, no switching;
PG open; no switching
EN = 0; V
CC
= 21 V; PG open
EN = 0;V
CC
= 4.5 V; PG open
FEEDBACK VOLTAGE
FB Input Voltage
VFB
T
J
= 25°C, 4.5 V
≤
VCC
≤
21 V
−40°C < TJ < 125°C; 4.5 V
≤
VCC
≤
21 V
Feedback Input Bias Current
ERROR AMPLIFIER
Open Loop DC Gain (GBD)
Open Loop Unity Gain Bandwidth
Open Loop Phase Margin
Slew Rate
COMP Clamp Voltage, High
COMP Clamp Voltage, Low
Output Source Current
Output Sink Current
CURRENT LIMIT
Low−side ISET Current Source
Low−side ISET Current Source
Temperature Coefficient
Low−side OCP Switch−over
Threshold
Low−side Fixed OCP Threshold
Low−side Programmable OCP
Range
LS OCP Blanking time
PWM
Maximum duty cycle
Minimum duty cycle
Minimum GH on−time
PWM Ramp Amplitude
PWM Ramp Offset
fsw = 500 kHz, VFB = 0 V
4.5 V < VCC < 21 V
VCOMP < PWM Ramp Offset Voltage
Guaranteed by characterization
Guaranteed by characterization
92
0
60
VCC/8.6 VCC/6.6 VCC/5.6
0.64
%
%
ns
V
V
LS_Tblnk
LS_OCPth
LS_ISET
TC_LS_I−
SET
Guaranteed by design
Guaranteed by design
Guaranteed by characterization
Guaranteed by design
150
Sourced from ISET pin, before SS,
T
J
= 25°C
30.5
33
+0.31
600
300
< 600
35.5
mA
%/°C
mV
mV
mV
ns
VFB = 0 V
VFB = 1 V
15
20
COMP pin to GND = 10 pF
F0dB,EA
60
85
24
60
2.5
3.4
0.465
dB
MHz
°
V/m
V
V
mA
mA
IFB
VFB = 0.6 V
0.597
0.594
0.6
0.6
0.603
0.606
75
nA
V
VIN/VCC
4.5
4.1
3.4
4.9
4.2
3.6
5.15
36
4.7
100
55
21
4.3
3.8
5.45
110
6.4
140
75
V
V
V
V
mV
mA
mA
mA
Symbol
Test Conditions
Min
Typ
Max
Unit
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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