19-5225; Rev 1; 9/10
KIT
ATION
EVALU
BLE
AVAILA
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
General Description
The MAX11644/MAX11645 low-power, 12-bit, 1-/2-
channel analog-to-digital converters (ADCs) feature
internal track/hold (T/H), voltage reference, clock, and
an I
2
C-compatible 2-wire serial interface. These
devices operate from a single supply of 2.7V to 3.6V
(MAX11645) or 4.5V to 5.5V (MAX11644) and require
only 6μA at a 1ksps sample rate. AutoShutdown™ pow-
ers down the devices between conversions, reducing
supply current to less than 1μA at low throughput rates.
The MAX11644/MAX11645 each measure two single-
ended or one differential input. The fully differential ana-
log inputs are software configurable for unipolar or
bipolar, and single-ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to V
DD
. The MAX11645 fea-
tures a 2.048V internal reference and the MAX11644
features a 4.096V internal reference.
The MAX11644/MAX11645 are available in an ultra-tiny
1.9mm x 2.2mm WLP package and an 8-pin μMAX
®
package. The MAX11644/MAX11645 are guaranteed
over the extended temperature range (-40°C to +85°C).
For pin-compatible 10-bit parts, refer to the MAX11646/
MAX11647 data sheet.
Features
♦
Ultra-Tiny 1.9mm x 2.2mm Wafer Level Package
♦
High-Speed I
2
C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
♦
Single-Supply
2.7V to 3.6V (MAX11645)
4.5V to 5.5V (MAX11644)
♦
Internal Reference
2.048V (MAX11645)
4.096V (MAX11644)
♦
External Reference: 1V to V
DD
♦
Internal Clock
2-Channel Single-Ended or 1-Channel Fully
Differential
♦
Internal FIFO with Channel-Scan Mode
♦
Low Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down Mode
♦
Software-Configurable Unipolar/Bipolar
MAX11644/MAX11645
Applications
Handheld Portable
Applications
Medical Instruments
Battery-Powered Test
Equipment
Solar-Powered Remote
Systems
Received-Signal-Strength
Indicators
System Supervision
Power-Supply Monitoring
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
8 μMAX
8 μMAX
12 WLP
I
2
C SLAVE
ADDRESS
0110110
0110110
0110110
MAX11644EUA+
-40°C to +85°C
MAX11645EUA+
-40°C to +85°C
MAX11645EWC+ -40°C to +85°C
+Denotes
a lead(Pb)-free/RoHs-compliant package.
Typical Operating Circuit and Selector Guide appear at end
of data sheet.
AutoShutdown is a trademark and μMAX is a registered trademark
of Maxim Integrated Products, Inc.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
MAX11644/MAX11645
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ..............................................................-0.3V to +6V
AIN0, AIN1, REF to GND ..............................-0.3V to the lower of
(V
DD
+ 0.3V) and 6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
8-Pin μMAX (derate 4.5mW/°C above +70°C) ..............362mW
12-Pin WLP (derate 16.1mW/°C above +70°C) ..........1288mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s)
μMAX only .....................................................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 2.7V to 3.6V (MAX11645), V
DD
= 4.5V to 5.5V (MAX11644), V
REF
= 2.048V (MAX11645), V
REF
= 4.096V (MAX11644),
f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
PARAMETER
DC ACCURACY (Note 2)
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Offset-Error Temperature
Coefficient
Gain Error
Gain-Temperature Coefficient
Channel-to-Channel Offset
Matching
Channel-to-Channel Gain
Matching
DYNAMIC PERFORMANCE (f
IN(SINE-WAVE)
= 10kHz, V
IN(P-P)
= V
REF
, f
SAMPLE
= 94.4ksps)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time (Note 5)
Throughput Rate
Track/Hold Acquisition Time
Internal Clock Frequency
Aperture Delay (Note 6)
t
AD
External clock, fast mode
External clock, high-speed mode
t
CONV
f
SAMPLE
Internal clock
External clock
Internal clock, SCAN[1:0] = 01
External clock
800
2.8
60
30
10.6
51
94.4
7.5
μs
ksps
ns
MHz
ns
SINAD
THD
SFDR
SINAD > 68dB
-3dB point
Up to the 5th harmonic
70
-78
78
3
5
dB
dB
dB
MHz
MHz
Relative to FSR
(Note 4)
Relative to FSR
0.3
±0.1
±0.1
0.3
±4
INL
DNL
(Note 3)
No missing codes over temperature
12
±1
±1
±4
Bits
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
LSB
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX11645), V
DD
= 4.5V to 5.5V (MAX11644), V
REF
= 2.048V (MAX11645), V
REF
= 4.096V (MAX11644),
f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
PARAMETER
ANALOG INPUT (AIN0/AIN1)
Input Voltage Range, Single-
Ended and Differential (Note 7)
Input Multiplexer Leakage
Input Capacitance
INTERNAL REFERENCE (Note 8)
Reference Voltage
Reference-Voltage Temperature
Coefficient
REF Short-Circuit Current
REF Source Impedance
EXTERNAL REFERENCE
REF Input Voltage Range
REF Input Current
Input-High Voltage
Input-Low Voltage
Input Hysteresis
Input Current
Input Capacitance
Output Low Voltage
POWER REQUIREMENTS
Supply Voltage
V
DD
MAX11645
MAX11644
f
SAMPLE
= 94.4ksps Internal reference
external clock
External reference
f
SAMPLE
= 40ksps
internal clock
Supply Current
I
DD
f
SAMPLE
= 10ksps
internal clock
f
SAMPLE
=1ksps
internal clock
Power-Supply Rejection Ratio
PSRR
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
2.7
4.5
900
670
530
230
380
60
330
6
0.5
±0.5
10
±2.0
LSB/V
μA
3.6
5.5
1150
900
V
V
REF
I
REF
V
IH
V
IL
V
HYST
I
IN
C
IN
V
OL
I
SINK
= 3mA
V
IN
= 0 to V
DD
15
0.4
0.1 x V
DD
±10
(Note 9)
f
SAMPLE
= 94.4ksps
0.7 x V
DD
0.3 x V
DD
1
V
DD
40
V
μA
V
V
V
μA
pF
V
1.5
V
REF
TCV
REF
T
A
= +25°C
MAX11645
MAX11644
1.968
3.936
2.048
4.096
25
2
2.128
4.256
V
ppm/°C
mA
k
C
IN
Unipolar
Bipolar
On/off leakage current, V
AIN
_ = 0 or V
DD
0
0
±0.01
22
V
REF
±V
REF
/2
±1
V
μA
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX11644/MAX11645
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Shutdown (internal REF off)
Full-scale input (Note 10)
_______________________________________________________________________________________
3
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
MAX11644/MAX11645
TIMING CHARACTERISTICS (Figure 1)
(V
DD
= 2.7V to 3.6V (MAX11645), V
DD
= 4.5V to 5.5V (MAX11644), V
REF
= 2.048V (MAX11645), V
REF
= 4.096V (MAX11644),
f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
PARAMETER
Serial-Clock Frequency
Bus Free Time Between a STOP (P)
and a START (S) Condition
Hold Time for START Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
(Sr) Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
Serial-Clock Frequency
Hold Time, Repeated START
Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
Condition
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
SYMBOL
f
SCL
t
BUF
t
HD,STA
t
LOW
t
HIGH
t
SU,STA
t
HD,DAT
t
SU,DAT
t
R
t
F
t
SU,STO
C
B
t
SP
f
SCLH
t
HD,STA
t
LOW
t
HIGH
t
SU
,
STA
t
HD
,
DAT
t
SU
,
DAT
t
RCL
(Note 11)
(Note 14)
160
320
120
160
0
10
20
80
150
Measured from 0.3V
DD
- 0.7V
DD
Measured from 0.3V
DD
- 0.7V
DD
(Note 12)
(Note 11)
1.3
0.6
1.3
0.6
0.6
0
100
20 + 0.1C
B
20 + 0.1C
B
0.6
400
50
1.7
300
300
900
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
μs
μs
μs
μs
μs
ns
ns
ns
ns
μs
pF
ns
MHz
ns
ns
ns
ns
ns
ns
ns
TIMING CHARACTERISTICS FOR FAST MODE
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C
B
= 400pF, Note 13)
4
_______________________________________________________________________________________
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.7V to 3.6V (MAX11645), V
DD
= 4.5V to 5.5V (MAX11644), V
REF
= 2.048V (MAX11645), V
REF
= 4.096V (MAX11644),
f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
PARAMETER
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
SYMBOL
t
RCL1
t
FCL
t
RDA
t
FDA
t
SU
,
STO
C
B
t
SP
(Notes 11 and 14)
CONDITIONS
Measured from 0.3V
DD
- 0.7V
DD
Measured from 0.3V
DD
- 0.7V
DD
Measured from 0.3V
DD
- 0.7V
DD
Measured from 0.3V
DD
- 0.7V
DD
(Note 12)
MIN
20
20
20
20
160
400
0
10
TYP
MAX
160
80
160
160
UNITS
ns
ns
ns
ns
ns
pF
ns
MAX11644/MAX11645
All WLP devices are 100% production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2:
For DC accuracy, the MAX11644 is tested at VDD = 5V and the MAX11645 is tested at VDD = 3V with an external
reference for both ADCs. All devices are configured for unipolar, single-ended inputs.
Note 3:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4:
Offset nulled.
Note 5:
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6:
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7:
The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to V
DD
.
Note 8:
When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a
0.1μF capacitor and a 2kΩ series resistor (see the
Typical Operating Circuit).
Note 9:
ADC performance is limited by the converter’s noise floor, typically 300μV
P-P
.
Note 10:
Measured for the MAX11645 as:
Note 1:
⎡
2
N
⎢ ⎡
V
FS
(3.6V)
−
V
FS
(2.7V)
⎤ ×
⎣
⎦
V
REF
⎢
⎣
(3.6V
−
2.7V)
⎤
⎥
⎥
⎦
and for the MAX11644, where N is the number of bits:
⎡
2
N
⎢ ⎡
V
FS
(5.5V)
−
V
FS
(4.5V)
⎤ ×
⎣
⎦
V
REF
⎢
⎣
(5.5V
−
4.5V)
⎤
⎥
⎥
⎦
Note 11:
A master device must provide a data hold time for SDA (referred to V
IL
of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12:
The minimum value is specified at T
A
= +25°C.
Note 13:
C
B
= total capacitance of one bus line in pF.
Note 14:
f
SCL
must meet the minimum clock low time plus the rise/fall times.
_______________________________________________________________________________________
5
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