rating of 1.5 kV rms to 6.0 kV rms and the data rate from DC up
to 600Mbps (see the Ordering Guide). The devices operate with
the supply voltage on either side ranging from 3.0 V to 5.5 V,
providing compatibility with lower voltage systems as well as
enabling voltage translation functionality across the isolation
barrier. The fail-safe state is available in which the outputs
transition to a preset state when the input power supply is not
applied.
π13xUxx:
150kbps
High common-mode transient immunity: 150 kV/µs typical
High robustness to radiated and conducted noise
Isolation voltages:
π13xx3x:
AC 3000Vrms
π13xx6x:
AC 6000Vrms
High ESD rating:
ESDA/JEDEC JS-001-2017
Human body model (HBM) ±8kV, all pins
Safety and regulatory approvals (Pending)：
UL certificate number: E494497
3000Vrms/6000Vrms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate number: 40047929
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
V
IORM
= 707V peak/1200V peak
CQC certification per GB4943.1-2011
3 V to 5.5 V level translation
AEC-Q100 qualification
Wide temperature range: -40°C to 125°C
16-lead, RoHS-compliant, SOIC_N, SOIC_W and SSOP package
FUNCTIONAL BLOCK DIAGRAMS
V
DD1
GND
1
V
IA
V
IB
V
IC
1
2
π130X3X
16
V
DD2
GND
2
V
DD1
GND
1
V
IA
V
IB
1
2
3
4
5
π130X6X
16
15
V
DD2
15
14
13
GND
2
V
OA
V
OB
V
OC
NC
3
4
5
6
V
OA
V
OB
V
OC
NC
14
13
12
11
10
12
11
10
V
IC
NC
NC
GND
1
NC
6
NC
7
7
8
NC
GND
2
EN2
9
GND
1
8
9
GND
2
V
DD1
GND
1
1
2
3
4
5
6
7
8
π131X3X
16
15
V
DD2
V
DD1
GND
1
V
IA
1
2
π131X6X
16
15
14
13
12
V
DD
2
GND
2
V
OA
V
OB
V
IC
GND
2
V
OA
V
OB
V
IA
V
IB
V
OC
14
13
12
11
3
4
5
V
IB
V
OC
NC
V
IC
NC
EN2
NC
NC
GND
1
NC
NC
GND
2
6
11
10
9
10
9
EN1
7
GND
1
8
GND
2
APPLICATIONS
General-purpose multichannel isolation
Industrial field bus isolation
Figure1.
π130xxx/π131xxx
functional Block Diagram
V
DD1
V
DD2
GENERAL DESCRIPTION
The
π1xxxxx
is a 2PaiSemi digital isolators product family that
includes over hundreds of digital isolator products. By using
maturated standard semiconductor CMOS technology and
2PaiSEMI
iDivider
technology, these isolation components
provide outstanding performance characteristics and reliability
superior to alternatives such as optocoupler devices and other
integrated isolators.
Intelligent voltage divider technology (iDivider technology) is a
new generation digital isolator technology invented by 2PaiSEMI.
It uses the principle of capacitor voltage divider to transmit
voltage signal directly cross the isolator capacitor without signal
modulation and demodulation.
The
π1xxxxx isolator
data channels are independent and are
available in a variety of configurations with a withstand voltage
C
IN
0.1uF
C
OUT
0.1uF
VIN_A
VIN_B
VIN_C
1
2
3
4
5
6
7
8
GND
1
V
DD1
GND
1
V
IA
V
IB
V
IC
NC
NC
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
NC
NC
GND
2
16
15
14
13
12
11
10
9
GND
2
VOUT_A
VOUT_B
VOUT_C
Figure2.
π130x3x
Typical Application Circuit
Rev.1
Information furnished by 2Pai semi is believed to be accurate and reliable. However, no
responsibility is assumed by 2Pai semi for its use, nor for any infringements of patents or
other rights of third parties that may result from its use. Specifications subject to change
without notice. No license is granted by implication or otherwise under any patent or
patent rights of 2Pai semi.
Trademarks and registered trademarks are the property of their respective owners.
Room 308-309, No.22, Boxia Road, Pudong New District, Shanghai, 201203, China
021-50850681
2Pai Semiconductor Co., Limited. All rights reserved.
http://www.rpsemi.com/
Data Sheet
PIN CONFIGURATIONS AND FUNCTIONS
π130Uxx
Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Name
V
DD1
GND
1
V
IA
V
IB
V
IC
NC
NC
GND
1
GND
2
NC/EN2
Description
Supply Voltage for Isolator Side 1.
Ground 1. This pin is the ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
No connect.
No connect.
Ground 1. This pin is the ground reference for Isolator Side 1.
Ground 2. This pin is the ground reference for Isolator Side 2.
No connect for
π130U3X.
Output enable for
π130U6X.
Output pins on side 2 are
enabled when EN2 is high or open and in high-impedance
state when EN2 is low.
No connect.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. This pin is the ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2.
1
π130U/π131U
DD1
1
DD2
2
IA
IB
IC
OA
OB
OC
/EN2
2
Figure3
π130Uxx
Pin Configuration
11
12
13
14
15
16
NC
V
OC
V
OB
V
OA
GND
2
V
DD2
π131Uxx
Pin Function Descriptions
Pin No. Name Description
1
2
3
4
5
6
7
V
DD1
GND
1
V
IA
V
IB
V
OC
NC
NC
Supply Voltage for Isolator Side 1.
Ground 1. This pin is the ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Output C.
No connect.
No connect
for π131U3X.
Output enable for
π131U6X.
Output pins on side 1 are enabled
when EN1 is high or open and in high-impedance state when
EN1 is low.
Ground 1. This pin is the ground reference for Isolator Side 1.
Ground 2. This pin is the ground reference for Isolator Side 2.
No connect for
π131U3X.
Output enable for
π131U6X.
Output pins on side 2 are enabled
when EN2 is high or open and in high-impedance state when
EN2 is low.
No connect.
Logic Input C.
Logic Output B.
Logic Output A.
Ground 2. This pin is the ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2.
/EN1
1
DD1
1
DD2
2
IA
IB
OC
OA
OB
IC
/EN2
2
8
9
10
GND
1
GND
2
NC
Figure4
.
π131Uxx
Pin Configuration
11
12
13
14
15
16
NC
V
IC
V
OB
V
OA
GND
2
V
DD2
Rev. 1 | Page 2 of 15
Data Sheet
ABSOLUTE MAXIMUM RATINGS
T
A
= 25° unless otherwise noted.
C,
Table 1. Absolute Maximum Ratings
4
Parameter
Supply Voltages (V
DD1
-GND
1
, V
DD2
-GND
2
)
Input Voltages (V
IA
, V
IB
)
1
Output Voltages (V
OA
, V
OB
)
1
Average Output Current per Pin
2
Side 1 Output Current (I
O1
)
Average Output Current per Pin
2
Side 2 Output Current (I
O2
)
Common-Mode Transients Immunity
3
Storage Temperature (T
ST
) Range
Ambient Operating Temperature (T
A
) Range
Rating
−0.5
V to +7.0 V
−0.5
V to V
DDx
+ 0.5 V
−0.5
V to V
DDx
+ 0.5 V
−10
mA to +10 mA
−10
mA to +10 mA
−150
kV/µs to +150 kV/µs
−65°C
to +150°C
−40°C
to +125°C
π130U/π131U
Notes:
1
V
DDx
is the side voltage power supply V
DD
, where x = 1 or 2.
2
See Figure 6 for the maximum rated current values for various temperatures.
3
See Figure 16 for Common-mode transient immunity (CMTI) measurement.
4
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating
conditions for extended periods may affect product reliability.
RECOMMENDED OPERATING CONDITIONS
Table 2. Recommended Operating Conditions
Parameter
Supply Voltage
High Level Input Signal Voltage
Low Level Input Signal Voltage
High Level Output Current
Low Level Output Current
Maximum Data Rate
Junction Temperature
Ambient Operating Temperature
Notes:
1
V
DDx
is the side voltage power supply V
DD
, where x = 1 or 2.
Symbol
V
DDx 1
V
IH
V
IL
I
OH
I
OL
Min
3
0.7*V
DDx1
0
-6
Typ
Max
5.5
V
DDx1
0.3*V
DDx1
6
Unit
V
V
V
mA
mA
Kbps
°C
°C
0
T
J
T
A
-40
-40
150
150
125
Truth Tables
Table 3.
π130U3x/π131U3x
Truth Table
V
Ix
Input
1
Low
High
Open
Don’t Care
4
Don’t Care
4
V
DDI
State
1
Powered
2
Powered
2
Powered
2
Unpowered
3
Powered
2
V
DDO
State
1
Powered
2
Powered
2
Powered
2
Powered
2
Unpowered
3
Default Low
V
Ox
Output
1
Low
High
Low
Low
High Impedance
Default High
V
Ox
Output
1
Low
High
High
High
High Impedance
Test Conditions
/Comments
Normal operation
Normal operation
Default output
Default output
5
Notes:
1
V
Ix
/V
Ox
are the input/output signals of a given channel (A or B). V
DDI
/V
DDO
are the supply voltages on the input/output signal sides of this given channel.
Rev. 1 | Page 3 of 15
Data Sheet
2
Powered
3
Unpowered
π130U/π131U
means V
DDx
≥ 2.9 V
means V
DDx
< 2.3V
4
Input signal (V
Ix
) must be in a low state to avoid powering the given V
DDI1
through its ESD protection circuitry.
5
If the V
DDI
goes into unpowered status, the channel outputs the default logic signal after around 1us. If the V
DDI
goes into powered status, the channel outputs the input
status logic signal after around
3us.
Table 4.
π130U6x/π131U6x
Truth Table
V
Ix
Input
1
Low
High
Don’t Care
4
Open
Don’t Care
4
Don’t Care
4
Don’t Care
4
EN1/2 State
High or NC
High or NC
L
High or NC
High or NC
L
Don’t
Care
4
V
DDI
State
1
Powered
2
Powered
2
Powered
2
Powered
2
Unpowered
3
Unpowered
3
Powered
2
V
DDO
State
1
Powered
2
Powered
2
Powered
2
Powered
2
Powered
2
Powered
2
Unpowered
3
Default Low
V
Ox
Output
1
Low
High
High Impedance
Low
Low
High Impedance
High Impedance
Default High
V
Ox
Output
1
Low
High
High Impedance
High
High
High Impedance
High Impedance
Test Conditions
/Comments
Normal operation
Normal operation
Disabled
Default output
5
Default output
5
Notes:
1
V
Ix
/V
Ox
are the input/output signals of a given channel (A or B). V
DDI
/V
DDO
are the supply voltages on the input/output signal sides of this given channel.
2
Powered means V
DDx
≥ 2.9 V
3
Unpowered means V
DDx
< 2.3V
4
Input signal (V
Ix
) must be in a low state to avoid powering the given V
DDI1
through its ESD protection circuitry.
5
If the V
DDI
goes into unpowered status, the channel outputs the default logic signal after around 1us. If the V
DDI
goes into powered status, the channel outputs the input
status logic signal after around
3us.
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Table 5. Switching Specifications
V
DD1
- V
GND1
= V
DD2
- V
GND2
= 3.3V
DC
±
10% or 5V
DC
±
10%, T
A
=25°
unless otherwise noted.
C,
Parameter
Minimum Pulse Width
Maximum Data Rate
Propagation Delay Time
1,4
t
pHL
, t
pLH
Symbol
PW
150
3.0
3.2
Pulse Width Distortion
4
PWD
0
0
Part to Part Propagation Delay
Skew
4
t
PSK
0.02
0.02
4.5
4.8
0.2
0.2
0.3
0.3
Channel to Channel Propagation
Delay Skew
4
t
CSK
0
0
Output Signal Rise/Fall Time
4
Common-Mode Transient
Immunity
3
ESD（HBM - Human body
model）
t
r
/t
f
CMTI
ESD
100
1.5
150
±8
0.2
0.2
Min
Typ
Max
6.5
us
Kbps
us
us
us
us
us
us
us
us
ns
kV/µs
kV
Unit
Test Conditions/Comments
Within pulse width distortion (PWD) limit
Within PWD limit
The different time between 50% input signal to
50% output signal 50% @ 5V
DC
supply
@ 3.3V
DC
supply
The max different time between t
pHL
and t
pLH
@
5V
DC
supply. And The value is | t
pHL
- t
pLH
|
@ 3.3V
DC
supply
The max different propagation delay time
between any two devices at the same
temperature, load and voltage @ 5V
DC
supply
@ 3.3V
DC
supply
The max amount propagation delay time
differs between any two output channels in
the single device @ 5V
DC
supply.
@ 3.3V
DC
supply
10% to 90% signal terminated 50，See
figure13.
V
IN
= V
DDx2
or 0V, V
CM
= 1000 V
All pins
Rev. 1 | Page 4 of 15
Data Sheet
Notes:
1
t
pLH
= low-to-high propagation delay time, t
pHL
= high-to-low propagation delay time. See figure 14.
2
V
DDx
is the side voltage power supply V
DD
, where x = 1 or 2.
3
See Figure 16 for Common-mode transient immunity (CMTI) measurement.
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