* The curves shown are typical for the highest voltage device in the voltage
grouping. Typical reverse current for lower voltage selections can be estim
ated from these same curves if applied V
R
is sufficiently below rated V
R
.
1000
I
R
, REVERSE CURRENT (mA)
T
J
= 175°C
100
T
J
= 150°C
10
T
J
= 100°C
Figure 4. Maximum Reverse Current for
MURS230T3
1
T
J
= 25°C
0.1
0
50
100
150
200
250
300
350
400
V
R
, REVERSE VOLTAGE (VOLTS)
Figure 5. Maximum Reverse Current for
MURS240T3
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3
MURS230T3, MURS240T3
30
25
C, CAPACITANCE (pF)
20
15
10
5
0
0
4.0
8.0
12
16
20
24
28
32
36
40
V
R
, REVERSE VOLTAGE (VOLTS)
NOTE: TYPICAL
CAPACITANCE AT
0 V = 26 pF
35
30
C, CAPACITANCE (pF)
25
20
15
10
5
0
0
4
8
12
16
20
24
28
32
36
40
V
R
, REVERSE VOLTAGE (VOLTS)
NOTE: MAXIMUM
CAPACITANCE AT
0 V = 30 pF
Figure 6. Typical Capacitance
Figure 7. Maximum Capacitance
IF(AV) , AVERAGE FORWARD CURRENT (AMPS)
10
9
8
7
6
5
4
3
2
1
0
80
90
100
110
120
130
140
150
160
170
180
T
C
, CASE TEMPERATURE (°C)
SQUARE WAVE
dc
RATED VOLTAGE APPLIED
R
qJL
= 13°C/W
T
J
= 175°C
PF(AV) , AVERAGE POWER DISSIPATION (WATTS)
5
T
J
= 175°C
4
3
SQUARE WAVE
dc
1
0
0
0.5
1.0
1.5
2.0
2.5
I
F(AV)
, AVERAGE FORWARD CURRENT (AMPS)
2
Figure 8. Current Derating, Case
Figure 9. Power Dissipation
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4
MURS230T3, MURS240T3
PACKAGE DIMENSIONS
SMB
CASE 403A−03
ISSUE G
H
E
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. D DIMENSION SHALL BE MEASURED WITHIN DIMENSION P.
DIM
A
A1
b
c
D
E
H
E
L
L1
MIN
1.90
0.05
1.96
0.15
3.30
4.06
5.21
0.76
MILLIMETERS
NOM
MAX
2.13
2.45
0.10
0.20
2.03
2.20
0.23
0.31
3.56
3.95
4.32
4.60
5.44
5.60
1.02
1.60
0.51 REF
MIN
0.075
0.002
0.077
0.006
0.130
0.160
0.205
0.030
INCHES
NOM
0.084
0.004
0.080
0.009
0.140
0.170
0.214
0.040
0.020 REF
MAX
0.096
0.008
0.087
0.012
0.156
0.181
0.220
0.063
b
D
A
L
L1
c
A1
SOLDERING FOOTPRINT*
2.261
0.089
2.743
0.108
2.159
0.085
SCALE 8:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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