®
HS-82C85RH
Data Sheet
April 20, 2007
FN3044.3
Radiation Hardened CMOS Static Clock
Controller/Generator
The Intersil HS-82C85RH is a high performance, radiation
hardened CMOS Clock Controller/Generator designed to
support systems utilizing radiation hardened static CMOS
microprocessors such as the HS-80C86RH. The
HS-82C85RH contains a crystal controlled oscillator, reset
pulse conditioning, halt/restart logic, and divide-by-256
circuitry. These features provide the means to stop the
system clock, stop the clock oscillator, or run the system at a
low frequency (CLK/256), enhancing control of static system
power dissipation and allowing system shut-down during
periods of external stress.
Static CMOS circuit design insures low operating power and
permits operation with an external frequency source from
DC to 15MHz. Crystal controlled operation to 15MHz is
guaranteed with the use of a parallel, fundamental mode
crystal and two small load capacitors. Outputs are
guaranteed compatible with both CMOS and TTL
specifications. The Intersil hardened field CMOS process
results in performance equal to or greater than existing
radiation resistant products at a fraction of the power.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95820. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/military/
Features
• Electrically Screened to SMD # 5962-95820
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . . . .>10
8
rad(Si)/s
- Latch Up Free EPI-CMOS
• Very Low Power Consumption
• Pin Compatible with NMOS 8285 and Intersil 82C85
• Generates System Clocks for Microprocessors and
Peripherals
• Complete Control Over System Clock Operation for Very
Low System Power
- Stop-Oscillator
- Stop-Clock
- Low Frequency (Slo) Mode
- Full Speed Operation
• DC to 15MHz Operation (DC to 5MHz System Clock)
• Generates Both 50% and 33% Duty Cycle Clocks
(Synchronized)
• Uses Either Parallel Mode Crystal Circuit or External
Frequency Source
• Hardened Field, Self-Aligned, Junction Isolated CMOS
Process
• Single 5V Supply
• Military Temperature Range . . . . . . . . . . . -55°C to +125°C
Ordering Information
ORDERING NUMBER
5962R9582001VJC
5962R9582001VXC
5962R9582001QJC
5962R9582001QXC
INTERNAL
MKT. NUMBER
HS1-82C85RH-Q
HS9-82C85RH-Q
HS1-82C85RH-8
HS9-82C85RH-8
PART MARKING
Q 5962R95 82001VJC
Q 5962R95 82001VXC
Q 5962R95 82001VJC
Q 5962R95 82001VXC
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
24 Ld SBDIP
24 Ld Flatpack
24 Ld SBDIP
24 Ld Flatpack
PKG. DWG. #
D24.6
K24.A
D24.6
K24.A
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HS-82C85RH
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
CLK50 10
START 11
SLO/FST 12
24 V
DD
23 X1
22 X2
21 ASYNC
20 EFI
19 F/C
18 OSC
17 RES
16 RESET
15 S2/STOP
14 S1
13 S0
24 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
CSYNC
PCLK
AEN1
RDY1
READY
RDY2
AEN2
CLK
GND
CLK50
START
SLO/FST
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
DD
X1
X2
ASYNC
EFI
F/C
OSC
RES
RESET
S2/STOP
S1
S0
Pin Descriptions
PIN
X1
X2
EFI
PIN
NUMBER
23
22
20
TYPE
I
O
I
DESCRIPTION
CRYSTAL CONNECTIONS: X1 and X2 are the crystal oscillator connections. The crystal frequency must
be three times the maximum desired processor clock frequency. X1 is the oscillator circuit input and X2
is the output of the oscillator circuit.
EXTERNAL FREQUENCY IN: When F/C is HIGH, CLK is generated from the EFI input signal. This input
signal should be a square wave with a frequency of three times the maximum desired CLK output
frequency.
FREQUENCY/CRYSTAL SELECT: F/C selects either the crystal oscillator or the EFI input as the main
frequency source. When F/C is LOW, the HS-82C85RH clocks are derived from the crystal oscillator
circuit. When F/C is HIGH, CLK is generated from the EFI input. F/C cannot be dynamically switched
during normal operation.
A low-to-high transition on START will restart the CLK, CLK50 and PCLK outputs after the appropriate
restart sequence is completed.
When in the crystal mode (F/C LOW) with the oscillator stopped, the oscillator will be restarted when a
Start command is received. The CLK, CLK50 and PCLK outputs will start after the oscillator input signal
(X1) reaches the Schmitt trigger input threshold and an 8K internal counter reaches terminal count. If F/C
is HIGH (EFI mode), CLK, CLK50 and PCLK will restart within 3 EFI cycles after START is recognized.
The HS-82C85RH will restart in the same mode (SLO/FST) in which it stopped. A high level on START
disables the STOP mode.
S2/STOP, S1, S0 are used to stop the HS-82C85RH clock outputs (CLK, CLK50, PCLK) and are sampled
by the rising edge of CLK. CLK, CLK50 and PCLK are stopped by S2/STOP, S1, S0 being in the LHH
state on the low-to-high transition of CLK. This LHH state must follow a passive HHH state occurring on
the previous low-to-high CLK transition. CLK and CLK50 stop in the high state. PCLK stops in it’s current
state (high or low).
When in the crystal mode (F/C) low and a STOP command is issued, the HS-82C85RH oscillator will stop
along with the CLK, CLK50 and PCLK outputs. When in the EFI mode, only the CLK, CLK50 and PCLK
outputs will be halted. The oscillator circuit if operational, will continue to run. The oscillator and/or clock
is restarted by the START input signal going true (HIGH) or the reset input (RES) going low.
F/C
19
I
START
11
I
S0
S1
S2/STOP
13
14
15
I
I
I
2
FN3044.3
April 20, 2007
HS-82C85RH
Pin Descriptions
PIN
SLO/FST
PIN
NUMBER
12
(Continued)
TYPE
I
DESCRIPTION
SLO/FST is a level-triggered input. When HIGH, the CLK and CLK50 outputs run at the maximum
frequency (crystal or EFI frequency divided by 3). When LOW, CLK and CLK50 frequencies are equal to
the crystal or EFI frequency divided by 768. SLO/FST mode changes are internally synchronized to
eliminate glitches on the CLK and CLK50. START and STOP control of the oscillator or EFI is available
in either the SLOW or FAST frequency modes.
The SLO/FST input must be held LOW for at least 195 OSC/EFI clock cycles before it will be recognized.
This eliminates unwanted frequency changes which could be caused by glitches or noise transients. The
SLO/FST input must be held HIGH for at least 6 OSC/EFI clock pulses to guarantee a transition to FAST
mode operation.
PROCESSOR CLOCK: CLK is the clock output used by the HS-80C86RH processor and other
peripheral devices. When SLO/FST is high, CLK has an output frequency which is equal to the crystal or
EFI input frequency divided by three. When SLO/FST is low, CLK has an output frequency which is equal
to the crystal or EFI input frequency divide by 768. CLK has a 33% duty cycle.
50% DUTY CYCLE CLOCK: CLK50 is an auxiliary clock with a 50% duty cycle and is synchronized to
the falling edge of CLK. When SLO/FST is high, CLK50 has an output frequency which is equal to the
crystal or EFI input frequency divided by 3. When SLO/FST is low, CLK50 has an output frequency equal
to the crystal or EFI input frequency divided by 768.
PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is equal to the crystal
or EFI input frequency divided by six and has a 50% duty cycle. PCLK frequency is unaffected by the
state of the SLO/FST input.
OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to that
of the crystal oscillator circuit. OSC is unaffected by the state of the SLO/FST input.
When the HS-82C85RH is in the crystal mode (F/C LOW) and a STOP command is issued, the OSC
output will stop in the HIGH state. When the HS-82C85RH is in the EFI mode (F/C HIGH), the oscillator
(if operational) will continue to run when a STOP command is issued and OSC remains active.
RESET IN: RES is an active LOW signal which is used to generate RESET. The HS-82C85RH provides
a Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper
duration. RES starts crystal oscillator operation.
RESET: RESET is an active HIGH signal which is used to reset the HS-80C86RH processor. Its timing
characteristics are determined by RES. RESET is guaranteed to be HIGH for a minimum of 16 CLK
pulses after the rising edge of RES.
CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple HS-82C85RHs to
be synchronized to provide multiple in-phase clock signals. When CSYNC is HIGH, the internal counters
are reset and force CLK, CLK50 and PCLK into a HIGH state. When CSYNC is LOW, the internal
counters are allowed to count and the CLK, CLK50 and PCLK outputs are active. CSYNC must be
externally synchronized to EFI.
ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready
Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are
useful in system configurations which permit the processor to access two Multi-Master System Buses.
BUS READY: (Transfer Complete). RDY is an active HIGH signal which is an indication from a device
located on the system data bus that data has been received, or is available. RDY1 is qualified by AEN1
while RDY2 is qualified by AEN2.
READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of
the READY logic. When ASYNC is LOW, two stages of READY synchronization are provided. When
ASYNC is left open or HIGH a single stage of READY synchronization is provided.
READY: READY is an active HIGH signal which is used to inform the HS-80C86RH that it may conclude
a pending data transfer.
Ground
+5V power supply
CLK
8
O
CLK50
10
O
PCLK
2
O
OSC
18
O
RES
17
I
RESET
16
O
CSYNC
1
I
AEN1
AEN2
RDY1
RDY2
ASYNC
3
7
4
6
21
I
I
I
I
I
READY
GND
V
DD
5
9
24
O
I
I
3
FN3044.3
April 20, 2007
HS-82C85RH
Functional Diagram
RES (17)
RESTART
LOGIC
RESET PULSE
CONDITIONING
LOGIC
RESTART
(16) RESET
START (11)
CSYNC (1)
SYNC
LOGIC
SYNC
CLOCK
LOGIC
(
÷
3)
(8) CLK
SLO/FST (12)
F/C (19)
EFI (20)
X2 (22)
X1 (23)
S2/STOP (15)
S1 (14)
SO (13)
RDY1 (4)
AEN1 (3)
AEN2 (7)
RDY2 (6)
ASYNC (21)
READY
SELECT
STOP
LOGIC
HALT
OSCILLATOR
EXTERNAL
FREQUENCY
SELECT
OSC
SPEED SELECT
÷
256 OR
÷
1
MASTER
OSC
PERIPHERAL
CLOCK
(
÷
6)
(10) CLK50
SELECTED OSC
(2) PCLK
(18) OSC
READY
SYNC
(24) V
DD
(9) GND
(5) READY
AC Test Circuit
V
DD
R (NOTES 1, 2)
FROM OUTPUT
UNDER TEST
C
L
(NOTE 4)
NOTES:
1. R = 370Ω at V = 2.25 for CLK and CLK50 outputs.
2. R = 494Ω at V = 2.87 for all other outputs.
3. C
L
= 50pF.
4. C
L
Includes probe and jig capacitance.
4
FN3044.3
April 20, 2007
HS-82C85RH
Waveforms
t
ELEL
EFI I
t
ELEH
t
EHEL
OSC O
t
OHCL
t
OHCH
CLK O
t
CHCL
t
CLCH
t
CLCL
t
CLC50L
CLK50 O
t
5CHCL
T
CLPH
PCLK O
t
YHEH
CSYNC I
t
YHYL
t
EHYL
t
PHPL
t
PLPH
t
CLPL
t
5CLCH
3.5V
1.0V
t
CL2CL1
t
OLCH
CLK AND CLK50
t
CH1CH2
FIGURE 1. WAVEFORMS FOR CLOCKS
NOTE: All timing measurements are made at 1.5V, unless otherwise noted.
CLK
t
CLR1X
t
R1VCH
RDY1, 2
t
A1VR1V
AEN1, 2
t
CLA1X
t
CLR1X
t
R1VCL
t
AYVCL
ASYNC
t
CLAYX
READY
t
RYHCH
t
RYLCL
FIGURE 2. WAVEFORMS FOR READY SIGNALS (FOR ASYNCHRONOUS DEVICES)
5
FN3044.3
April 20, 2007
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