19-6313; Rev 0; 5/12
MAX5825PMB1 Peripheral Module
General Description
The MAX5825PMB1 peripheral module provides the nec-
essary hardware to interface the MAX5825 8-channel DAC
to any system that utilizes PmodK-compatible expansion
ports configurable for I
2
C communication. The IC features
eight independent 12-bit accurate internally buffered
voltage-output DAC channels. The IC also features an
internal reference that is selectable between 2.048V,
2.500V, and 4.096V (4.096V reference operation is not
supported with a standard 3.3V Pmod-port power supply).
S
Eight High-Accuracy DAC Channels
S
12-Bit Accuracy without Adjustment
S
Precision Voltage Reference Internal to the IC
S
Provision for Optional External Reference Input
S
Jumper-Selectable I
2
C Address Setting
S
6-Pin Pmod-Compatible Connector (I
2
C)
S
Secondary Header Allows Daisy-Chaining of
Additional Modules on the I
2
C Bus
S
Example Software Written in C for Portability
S
RoHS Compliant
S
Proven PCB Layout
S
Fully Assembled and Tested
Ordering Information
appears at end of data sheet.
Features
MAX5825PMB1 Peripheral Module
Pmod is a trademark of Digilent Inc.
_________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX5825PMB1 Peripheral Module
Component List
DESIGNATION
C1
QTY
1
DESCRIPTION
10FF
Q10%,
10V X5R ceramic
capacitor (0603)
TDK C2012X5R1A106K/1.25
2.2FF
Q10%,
10V X5R ceramic
capacitor (0603)
TDK C1608X5R1A225K/0.80
0.1FF
Q10%,
16V X7R ceramic
capacitors (0603)
Murata GRM188R71C104KA01D
4.7FF EMI filter (3-terminal
capacitor)
Murata NFM21PC475B1A3D
6-pin right-angle male header
DESIGNATION
J2
J3
JP1, JP2
R1–R4
R5–R9
R10
QTY
1
1
2
4
5
0
DESCRIPTION
8-pin (2 x 4) straight male header
14-pin (2 x 7) straight male
header
3-pin straight male headers
150I
Q5%
resistors (0603)
4.7kI
Q5%
resistors (0603)
Not installed, 100kI resistor
(0603)
Octal-channel, 12-bit buffered
DAC (20 TSSOP)
Maxim MAX5825AAUP+
Shorting jumpers
PCB: EPCB5825PM1
C2
1
C3, C4
2
U1
—
—
1
2
1
F1
J1
1
1
Component Suppliers
SUPPLIER
Murata Electronics North America, Inc.
TDK Corp.
PHONE
770-436-1300
847-803-6100
WEBSITE
www.murata-northamerica.com
www.component.tdk.com
Note:
Indicate that you are using the MAX5825PMB1 when contacting these component suppliers.
Detailed Description
The MAX5825PMB1 peripheral module can interface to
the host in one of two ways. It can plug directly into a
Pmod-compatible port (configured for I
2
C) through con-
nector J1, or in this case, other I
2
C boards can attach to
the same I
2
C bus through connector J2.
Alternatively, the peripheral module can connect to other
I
2
C-based Pmod modules using a 4-conductor ribbon
cable connecting to the J2 connector. In this situation,
pins 1-4 and 5-8 on J2 provide two connections to the
I
2
C bus, allowing the module to be inserted into an I
2
C
bus daisy-chain.
Table 1. Connector J1 (I
2
C Communication)
PIN
1
2
3
4
5
6
SIGNAL
LDAC
IRQ
SCL
SDA
GND
VDD
DESCRIPTION
Active-low asynchronous DAC load input
Active-low open-drain interrupt output.
IRQ
low indicates a watchdog timeout.
I
2
C serial clock
I
2
C serial data
Ground
Power supply
I
2
C Interface
I
2
C Interface (Daisy-Chaining Modules)
Table 2. Connector J2 (I
2
C Expansion)
PIN
1
2
3
4
5
6
7
8
SIGNAL
SCL
SDA
GND
VDD
SCL
SDA
GND
VDD
DESCRIPTION
I
2
C serial clock
I
2
C serial data
Ground
Power supply
2-wire serial clock. Same as pin 1 above.
2-wire serial data. Same as pin 2 above.
Ground
Power supply
Connector J1 provides connection of the module to the
Pmod host. The pin assignments and functions adhere
to the Pmod standard recommended by Digilent. See
Table 1.
The J2 connector allows the module to be connected
through a daisy-chain from another I
2
C module and/or
provide I
2
C and power connections to other I
2
C modules
on the same bus. See Table 2.
_________________________________________________________________
Maxim Integrated Products
2
MAX5825PMB1 Peripheral Module
I
2
C Addressing Options
Software and FPGA Code
The I
2
C slave address for the IC can be one of nine
different values, depending on the settings on jumpers
JP1 and JP2. Table 3 lists the settings of those jump-
ers and the corresponding values of the slave address
A[3:0]. Refer to the MAX5823/MAX5824/MAX5825 IC
data sheet for more information.
The IC implements pins that allow asynchronously updat-
ing of all DAC channels simultaneously (LDAC) and
simultaneously clearing all DAC channels to their default
state (CLR). The
CLR
pin is only available through the
external J3 connector. The
LDAC
signal is available from
either the Pmod connector (J1) or the external connector
(J3). The default source for
LDAC
is the Pmod connector
(J1). To control
LDAC
from the external connector (J3),
modify the solder link on the back of the board (labeled
LK1). The user is cautioned to ensure that only one
source for this signal is selected at any given time.
The J3 connector provides the DAC output voltages and
the external control inputs. See Table 4.
The IC features a pin-selectable DAC reset state using
the M/Z input. Upon a power-on reset, all CODE and
DAC data registers are reset to zero scale (M/Z = GND)
or midscale (M/Z = VDD). The board is shipped with R11
installed (0I) and R10 not installed, which sets M/Z to
GND. To change to M/Z = VDD, remove R11 and install
a suitable pullup resistor for R10. Refer to the MAX5823/
MAX5824/MAX5825 IC data sheet for more information.
External Control Signals
Example software and drivers are available that execute
directly without modification on several FPGA devel-
opment boards that support an integrated or synthe-
sized microprocessor. These boards include the Digilent
Nexys 3, Avnet LX9, and Avnet ZEDBoard, although
other platforms can be added over time. Maxim provides
complete Xilinx ISE projects containing HDL, Platform
Studio, and SDK projects. In addition, a synthesized bit
stream, ready for FPGA download, is provided for the
demonstration application.
The software project (for the SDK) contains several
source files intended to accelerate customer evalu-
ation and design. These include a base application
(maximModules.c) that demonstrates module function-
ality and uses an API interface (maximDeviceSpecific
Utilities.c) to set and access Maxim device functions
within a specific module.
The source code is written in standard ANSI C format, and
all API documentation including theory/operation, register
description, and function prototypes are documented in
the API interface file (maximDeviceSpecificUtilities.h & .c).
The complete software kit is available for download at
www.maxim-ic.com.
Quick start instructions are also
available as a separate document.
Reset State (M/Z Pin)
Table 4. Connector J3 (External Interface)
PIN
1
2
3
SIGNAL
VDD
LDACEXT
GND
CLR
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
REF
GND
DESCRIPTION
Supply voltage
Active-low asynchronous DAC load
input
Ground
Active-low asynchronous DAC clear
input
DAC channel 7 voltage output
DAC channel 6 voltage output
DAC channel 5 voltage output
DAC channel 4 voltage output
DAC channel 3 voltage output
DAC channel 2 voltage output
DAC channel 1 voltage output
DAC channel 0 voltage output
Reference voltage input/output
Ground
Table 3. I
2
C Slave Address LSBs
JP1 (ADDR1)
1-2 (VDD)
1-2 (VDD)
1-2 (VDD)
Open
Open
Open
2-3 (GND)
2-3 (GND)
2-3 (GND)
JP2 (ADDR0)
1-2 (VDD)
Open
2-3 (GND)
1-2 (VDD)
Open
2-3 (GND)
1-2 (VDD)
Open
2-3 (GND)
A3
1
1
1
1
1
1
0
0
0
A2
1
1
1
0
0
0
0
0
0
A1
1
1
0
1
1
0
1
1
0
A0
1
0
0
1
0
0
1
0
0
4
5
6
7
8
9
10
11
12
13
14
_________________________________________________________________
Maxim Integrated Products
3
MAX5825PMB1 Peripheral Module
J1
1
2
3
4
5
6
R1
R2
R3
R4
150
LDAC
150
IRQ
150
SCL
150
SDA
GND
F1
1
EMIFILT
3
VDD
C1
10uF
GND
I2C Expansion Connector
J2
1
2
3
4
5
6
7
8
R5
4.7k
R6
4.7k
VDD VDD
2
GND
C2
2.2uF
GND
GND
C4
0.1uF
VDD
U1
VDD
10
11
R7
4.7k
R8
4.7k
R9
4.7k
GND
19
VDD
VDDIO
GND
DAC0
DAC1
DAC2
LDAC
SDA
SCL
CLR
IRQ
18
15
14
17
16
20
12
13
JP1
VDD
GND
1
2
3
VDD
GND
JP2
1
2
3
LDAC
SDA
SCL
CLR
IRQ
M/Z
ADDR1
ADDR0
REF
DAC3
DAC4
DAC5
DAC6
DAC7
MAX5825
VDD
C3
2
3
4
5
6
7
8
9
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
0.1uF
Select LDAC Source
LDAC
LDACEXT
LK1
LINKB
VDD
VDD
GND
DAC7
DAC5
DAC3
DAC1
REF
J3
1
3
5
7
9
11
13
2
4
6
8
10
12
14
LDACEXT
CLR
DAC6
DAC4
DAC2
DAC0
GND
Do Not Install
R10
100k
GND
R11
0
Output Connector
1
REF
I2C Address Selection
Figure 1. MAX5825PMB11 Peripheral Module Schematic
_________________________________________________________________
Maxim Integrated Products
4
MAX5825PMB1 Peripheral Module
Figure 2. MAX5825PMB11 Peripheral Module Component Placement Guide—Component Side
Figure 3. MAX5825PMB11 Peripheral Module PCB Layout—Component Side
Figure 4. MAX5825PMB11 Peripheral Module PCB Layout—Inner Layer 1 (Ground)
_________________________________________________________________
Maxim Integrated Products
5
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