Ordering number : ENA2197
LC87F1K64A
CMOS IC
8-bit Microcontroller
with USB-host Controller
64K-byte Flash ROM / 8K-byte RAM / 48-pin
http://onsemi.com
Overview
The LC87F1K64A is an 8-bit microcontroller that, integrates on a single chip a number of hardware features such as
64K-byte flash ROM, 8192-byte RAM, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into
8-bit timers), a 16-bit timer (may be divided into 8-bit timers or PWMs), four 8-bit timers with a prescaler, a base timer
serving as a time-of-day clock, two channels of synchronous SIO interface with automatic data transfer capabilities, an
asynchronous/synchronous SIO interface, a single-master I
2
C/synchronous SIO interface, a UART interface (full
duplex), a full/low-speed USB interface (host control function) × 2 ports, a 12-bit 12-channel AD converter, two
channels of 12-bit PWM, a system clock frequency divider, an infrared remote control receiver circuit, an internal reset
circuit, and a 44-source 10-vector interrupt feature.
Features
■
Flash ROM
•
65536×8 bits
•
Capable of on-board programming with a wide range of
supply voltage from 3.0 to 5.5V
•
Block-erasable in 128-byte units
•
Data written in 2-byte units
•
8192×9 bits
•
SQFP48 (7×7): Lead-/halogen-free product
•
83.3ns (when CF=12MHz)
Note: The bus cycle time here refers to the ROM read
speed.
36
37
■
RAM
SQFP48(7X7)
■
Package Form
■
Bus Cycle Time
25
24
■
Minimum Instruction Cycle Time (tCYC)
•
250ns (when CF=12MHz)
48
1
0.5
(0.75)
12
0.18
13
7.0
9.0
1.7max
ORDERING INFORMATION
See detailed ordering and shipping information on page 35 of this data sheet.
0.1
(1.5)
SQFP48(7X7)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
July, 2013
ver.1.02
71713HKPC 20111124-S00003 No.A2197-1/35
0.5
9.0
7.0
0.15
LC87F1K64A
■
Ports
•
I/O ports
Ports whose input/output can be specified in 1-bit units:
•
USB ports
•
Dedicated oscillator ports
•
Input-only port (also used for the oscillator)
•
Reset pin
•
Power supply pins
34 (P00 to P07, P10 to P17, P20 to P25, P30 to P34,
P70 to P73, PWM0, PWM1, XT2)
4 (UHAD+, UHAD–, UHBD+, UHBD–)
2 (CF1, CF2)
1 (XT1)
1 (RES)
6 (VSS1 to 3, VDD1 to 3)
■
Timers
•
Timer 0: 16-bit timer/counter with 2 capture registers
Mode 0: 8-bit timer with an 8-bit programmable prescaler
(with two 8-bit capture registers)
×
2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler
(with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
•
Timer 1: 16-bit timer/counter that supports PWM/toggle output
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle output)
+ 8-bit timer/counter with an 8-bit prescaler (with toggle output)
Mode 1: 8-bit PWM with an 8-bit prescaler
×
2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle output)
(Toggle output also possible from low-order 8 bits.)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle output)
(Low-order 8 bits can be used as a PWM output.)
•
Timer 4: 8-bit timer with a 6-bit prescaler
•
Timer 5: 8-bit timer with a 6-bit prescaler
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
•
Base timer
1) The clock can be selected from among a subclock (32.768kHz crystal oscillator), low-speed RC
oscillator clock, system clock, and timer 0 prescaler output.
2) Interrupts programmable in 5 different time schemes.
■
Serial Interfaces
•
SIO0: Synchronous serial interface
1) LSB first/MSB first selectable
2) Transfer clock cycle: 4/3 to 512/3 tCYC
3) Continuous automatic data transmission (1 to 256 bits can be specified in 1-bit units)
(Suspension and resumption of data transfer possible in 1-byte units)
•
SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clock)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrate)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clock)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
•
SIO4: Synchronous serial interface
1) LSB first/MSB first selectable
2) Transfer clock cycle: 4/3 to 1020/3 tCYC
3) Continuous automatic data transmission (1 to 8192 bytes can be specified in 1-byte units)
(Suspension and resumption of data transmission possible in 1-byte units or in word units)
4) Clock polarity can be selected.
5) CRC16 calculator circuit built- in
•
SMIIC0: Single-master I
2
C/8-bit synchronous SIO
Mode 0: Communication in single-master mode.
Mode 1: 8-bit synchronous serial I/O (data MSB first)
No.A2197-2/35
LC87F1K64A
■
Full Duplex UART
1) Data length:
2) Stop bits:
3) Parity bits:
4) Baudrate:
7/8/9 bits selectable
1 bit (2 bits in continuous transmission mode)
None/even/odd selectable (for 8-bit data only)
16/3 to 8192/3 tCYC
■
AD Converter: 12 bits
×
12 channels
■
PWM: Variable frequency 12-bit PWM
×
2 channels
■
Infrared Remote Control Receiver Circuit
1) Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is selected
as the reference clock)
2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding.
3) X'tal HOLD mode release function
■
USB Interface (host control function)
×
2 ports
1) Supports full-speed (12Mbps) and low-speed (1.5Mbps) specifications.
2) Supports four transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer).
■
Audio Interface
1) Sampling frequencies (fs): 8kHz/11.025kHz/12kHz/16kHz/22.05kHz/24kHz/32kHz/44.1kHz/48kHz
2) Master clock:
256fs/384fs
3) Bit clock:
48fs/64fs
4) Data bit length:
16bits/18bits/20bits/24bits
5) LSB first/MSB first selectable.
6) Left justified/right justified/I2S format selectable
■
Watchdog Timer
•
External RC time constant type
1) Interrupt generation/reset generation selectable
2) Operation in HALT/HOLD mode can be selected from “continue operation” and “suspend operation.”
•
Internal timer type
1) Capable of generating a internal reset signal on an overflow of the timer running on the low-speed RC oscillator
clock, or subclock.
2) Operation in HALT/HOLD mode can be selected from among “continue count operation,” “suspend operation,”
and “retain the count value.”
■
Clock Output Function
1) Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as
the system clock.
2) Can output the source oscillator clock for the subclock.
No.A2197-3/35
LC87F1K64A
■
Interrupts
•
44 sources, 10 vectors
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt request of
the level equal to or lower than the current interrupt level is not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the lowest vector
address is given priority.
No.
1
2
3
4
5
6
7
8
9
10
Vector
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4/UHC-A bus active/UHC-B bus active/remote control receive
INT3/INT5/base timer
T0H/INT6/UHC-A device connected, disconnected, resumed
T1L/T1H/INT7/AIF start/SMIIC0/UHC-B device connected, disconnected, resumed
SIO0/UART1 reception completed
SIO1/SIO4/UART1 buffer empty/UART1 transmission completed/AIF end
ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC-STALL
Port 0/PWM0/PWM1/T4/T5/UHC-SOF
Interrupt Source
•
Priority levels X
>
H
>
L
•
When interrupts of the same level occur at the same time, the interrupt with the lowest vector address is given
priority.
■
Subroutine Stack Levels: Up to 4096 levels (The stack is allocated in RAM.)
■
High-speed Multiplication/Division Instructions
•
16 bits
×
8 bits
•
24 bits
×
16 bits
•
16 bits
÷
8 bits
•
24 bits
÷
16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
■
Oscillator Circuit and PLL
•
Medium-speed RC oscillator circuit (internal):
•
Low-speed RC oscillator circuit (internal):
•
CF oscillator circuit:
•
Crystal oscillator circuit:
•
PLL circuit (internal):
For system clock (approx. 1MHz)
For system clock, timer, and watchdog timer (approx. 30kHz)
For system clock
For system clock and time-of-day clock
For USB interface (see Fig. 5) and audio interface (see Fig. 6)
■
Internal Reset Functions
•
Power-on reset (POR) function
1) POR is activated at power-on.
2) POR release voltage can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and 4.35V)
by setting options.
•
Low voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a threshold level.
2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,
2.81V, 3.79V, and 4.28V) can be selected by setting options.
No.A2197-4/35
LC87F1K64A
■
Standby Function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillators do not stop automatically.
2) There are three ways of releasing HOLD mode.
(1) Setting the reset pin to a low level.
(2) Generating a reset signal by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
•
HOLD mode: Suspends instruction execution and operation of the peripheral circuits.
1) The PLL, CF, RC and crystal oscillators automatically stop operation.
Note: Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in standby mode
is also controlled.
2) There are five ways of releasing HOLD mode.
(1) Setting the reset pin to a low level
(2) Generating a reset signal by the watchdog timer or low-voltage detection
(3) Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins
* INT0 and INT1 HOLD mode release is available only when level detection is configured.
(4) Establishing an interrupt source at port 0
(5) Establishing an bus active interrupt source in the USB host control circuit
•
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer
and infrared remote control receiver circuit.
1) The PLL, CF and RC oscillators automatically stop operation.
Note: Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in standby mode
is also controlled.
Note: The low-speed RC oscillator retains the state that is established on entry into X'tal HOLD mode if the base
timer is running with the low-speed RC oscillator selected as the base timer input clock source.
2) The state of crystal oscillator established when the X'tal HOLD mode is entered is retained.
3) There are seven ways of releasing X'tal HOLD mode.
(1) Setting the reset pin to a low level
(2) Generating a reset signal by the watchdog timer or low-voltage detection
(3) Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins
* INT0 and INT1 X'tal HOLD mode release is available only when level detection is configured.
(4) Establishing an interrupt source at port 0
(5) Establishing an interrupt source in the base timer circuit
(6) Establishing an interrupt source in the infrared remote control receiver circuit
(7) Establishing an bus active interrupt source in the USB host control circuit
■
Development Tools
•
On-chip debugger: TCB87–Type B + LC87F1K64A or
TCB87–Type C (3-wire communication cable) + LC87F1K64A
■
Flash ROM Programming Board
Package
SQFP48 (7×7)
Programming Board
W87F55256SQ
No.A2197-5/35
stm32/stm8
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