to minimize resistive DC losses. Long-term hermeticity
is assured through use of parallel seam welded lid
attachment along with International Rectifier’s rugged
ceramic pin-to-package seal. Axial lead orientation
facilitates preferred bulkhead mounting to the principal
heat-dissipating surface.
Manufactured in a facility fully qualified to MIL-PRF-
38534, these converters are fabricated utilizing DSCC
qualified processes. For available screening options
refer to device screening table in the data sheet.
Variations in electrical, mechanical and screening
specifications may be accommodated. Contact IR Santa
Clara for special requirements.
28V Input, Triple Output
ARM
Features
n
n
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n
n
n
n
n
n
n
n
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Total Dose > 1MRad (Si)
SEE Hardened to LET up to 83 Mev
.
cm
2
/mg
Derated per MIL-STD-975 & MIL-STD-1547
Output Power Range 3 to 30 Watts
19 to 50 Volt Input Range
Input Undervoltage Lockout
High Electrical Efficiency > 80%
Full Performance from -55°C to +125°C
Continuous Short Circuit Protection
12.8 W / in
3
Output Power Density
True Hermetic Package
External Inhibit Port
Externally Synchronizable
Fault Tolerant Design
5V,
±
12V or 5V,
±
15V Outputs Available
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1
08/11/06
ARM28XXT Series
Specifications
Absolute Maximum Ratings
Input Voltage range
Minimum Output Current
-0.5V to +80VDC
Recommended Operating Conditions
Input Voltage range
+19V to +60VDC
+19V to +50V for full derating to MIL-STD-975
3.0W to 30W
-55°C to +125°C
-55°C to +85°C for full derating to MIL-STD-975
5% Maximum rated
Output Power
current, any Output
Soldering temperature
300°C for 10 seconds Operating case
temperature
Storage case temperature -65°C to +135°C
Electrical Performance
-55°C < T
CASE
< +125°C, V
IN
=28V, C
L
=0 unless otherwise specified.
Parameter
Output voltage accuracy
Symbol
V
OUT
I
OUT
= ±250mAdc, T
C
= +25°C ARM2812(dual)
I
OUT
= ±250mAdc, T
C
= +25°C ARM2815(dual)
Output power
Note 5
Output current
Note 5
P
OUT
I
OUT
19 Vdc< V
IN
< 50Vdc
(main)
19 Vdc< V
IN
< 50Vdc
(dual)
Line regulation
Note 3
VR
LINE
150 mAdc < I
OUT
< 3000 mAdc
19 Vdc< V
IN
< 50Vdc
±75 mAdc < I
OUT
< ±750 mAdc
150 mAdc < I
OUT
< 3000 mAdc
19 Vdc< V
IN
< 50Vdc
±75 mAdc < I
OUT
< ±750 mAdc
19 Vdc< V
IN
< 50Vdc
(dual)
Total regulation
VR
All conditions of Line, Load,
(main)
Cross Regulation, Aging,
Temperature and Radiation ARM2812(dual)
ARM2815(dual)
I
OUT
= minimum rated, Pin 3 open
Input current
Output ripple voltage
Note 6
Input ripple current
Note 6
Switching frequency
Efficiency
I
IN
Pin 3 shorted to pin 2 (disabled)
V
RIP
I
RIP
F
S
Eff
19 Vdc< V
IN
< 50Vdc
I
OUT
= 3000 mAdc (main), ±500 mAdc (dual)
19 Vdc< V
IN
< 50Vdc
I
OUT
= 3000 mAdc (main), ±500 mAdc (dual)
Sychronization input open. (pin 6)
I
OUT
= 3000 mAdc (main), ±500 mAdc (dual)
225
80
8.0
100
150
275
mV
p.p
mA
p.p
KHz
%
-500
4.8
±11.1
±13.9
+500
5.2
V
±12.9
±16.0
250
mA
(main)
(dual)
(main)
(dual)
(main)
Cross regulation
Note 8
VR
CROSS
75
-15
-60
-180
-300
-10
750
+15
mV
+60
+180
mV
+300
+10
mV
±11.50
±14.50
3.0
150
±12.50
±15.15
30
3000
mAdc
W
Conditions
I
OUT
= 1.5Adc, T
C
= +25°C
(main)
Min
4.95
Max
5.05
Vdc
Units
Load regulation
Note 4
VR
LOAD
For Notes to Specifications, refer to page 3
2
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ARM28XXT Series
Electrical Performance
(Continued)
Parameter
Enable Input
open circuit voltage
drive current (sink)
voltage range
Synchronization Input
frequency range
pulse high level
pulse low level
pulse rise time
pulse duty cycle
Power dissipation, load fault
Output response to step load
changes
Notes 7, 11
Recovery time from step load
changes
Notes 11, 12
Output response to step line
changes
Notes 10, 11
Recovery time from step line
changes
Notes 10, 11,13
P
D
V
TLD
50% Load to/from 100% load
10% Load to/from 50% load
T
TLD
50% Load to/from 100% load
V
TLN
I
OUT
= 3000 mAdc
V
IN
= 19 V to/from 50 V
I
OUT
= ±500 mAdc
I
OUT
= 3000 mAdc
V
IN
= 19 V to/from 50 V
I
OUT
= ±500 mAdc
I
OUT
= minimum and full rated
(dual)
Turn on delay
Note 14
Capacitive load
Notes 9, 10
Isolation
T
DLY
CL
ISO
I
OUT
= minimum and full rated
(main)
No effect on DC performance
(dual)
500VDC Input to Output or any pin to case
(except pin 12)
100
100
MΩ
5.0
1500
20
500
µF
ms
(main)
(dual)
(main)
(dual)
(main)
Turn on overshoot
V
OS
-350
-1050
200
350
mV
PK
1050
500
500
500
mV
µs
-200
200
200
µs
Symbol
Conditions
19 Vdc< V
IN
< 50Vdc
Min
3.0
0.1
-0.5
225
4.5
-0.5
40
20
Short circuit, any output
10% Load to/from 50% load
-200
Max
5.0
50.0
310
10.0
0.25
80
7.5
200
mV
PK
Units
V
mA
V
KHz
V
V
V/µs
%
W
External clock signal on Sync. input (pin 4)
T
TLN
Notes to Specifications Table
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Operation outside absolute maximum/minimum limits may cause permanent damage to the device. Extended operation at the limits may permanently
degrade performance and affect reliability.
Device performance specified in Electrical Performance table is guaranteed when operated within recommended limits. Operation outside
recommended limits is not specified.
Parameter measured from 28V to 19 V or to 50V while loads remain fixed.
Parameter measured from nominal to minimum or maximum load conditions while line remains fixed.
Up to 750 mA is available from the dual outputs provided the total output power does not exceed 30W.
Guaranteed for a bandwidth of DC to 20MHz. Tested using a 20KHz to 2MHz bandwidth.
Load current is stepped for output under test while other outputs are fixed at half rated load.
Load current is fixed for output under test while other output loads are varied for any combination of minimum to maximum.
A capacitive load of any value from 0 to the specified maximum is permitted without comprise to DC performance. A capacitive load in excess of the
maximum limit may interfere with the proper operation of the converter’s short circuit protection, causing erratic behavior during turn on.
Parameter is tested as part of design characterization or after design or process changes. Thereafter, parameters shall be guaranteed to the limits
specified in the table.
Load transient rate of change, di/dt
≤
2A/µs
.
2 A/µSec.
Recovery time is measured from the initiation of the transient to where V
OUT
has returned to within ±1% of its steady state value.
Line transient rate of change, dv/dt
≤
50V/µs.
50 V/µSec.
Turn on delay time is for either a step application of input power or a logical low to high transition on the enable pin (pin 3) while power is present at the
input.
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3
ARM28XXT Series
Group A Tests
V
IN
= 28Volts, C
L
=0 unless otherwise specified.
Test
Output voltage accuracy
Symbol
V
OUT
I
OUT
= ±250mAdc
I
OUT
= ±250mAdc
Output power
Note 1
Output current
Note 1
Output regulation
Note 4
P
OUT
I
OUT
V
IN
= 19 V, 28V, 50 V
(main)
V
IN
19 V, 28V, 50 V
(dual)
VR
I
OUT
= 150, 1500, 3000mAdc
V
IN
= 19 V, 28V, 50 V
I
OUT
= ±75, ±310, ±625mAdc
I
OUT
= ±75, ±250, ±500mAdc
(main)
2812(dual)
2815(dual)
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
4, 5, 6
1
2, 3
1, 2, 3
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
(main)
Turn on overshoot
Turn on delay
Note 7
Isolation
V
OS
T
DLY
ISO
I
OUT
= minimum and full rated
(dual)
I
OUT
= minimum and full rated
500VDC Input to output or any pin to case
(except pin 12)
4, 5, 6
4, 5, 6
1
5.0
100
1500
20
ms
MΩ
4, 5, 6
-200
-200
225
80
78
7.5
200
mV
PK
50% Load to/from 100% load
Recovery time from step
load changes
Notes 5, 6
10% Load to/from 50% load
T
TL
50% Load to/from 100% load
200
500
mV
200
200
µs
75
4.8
±11.1
±14.0
500
5.2
V
±12.9
±15.8
250
mA
Pin 3 shorted to pin 2 (disabled)
Output ripple
Note 2
Input ripple
Note 2
Switching frequency
Efficiency
Power dissipation,
load fault
Output response to step
load changes
Notes 3, 5
V
RIP
I
RIP
F
S
Eff
P
D
V
IN
= 19 V, 28V, 50 V
I
OUT
= 3000mA main, ±500mA dual
V
IN
= 19 V, 28V, 50 V
I
OUT
= 3000mA main, ±500mA dual
Synchronization pin (pin 6) open
I
OUT
= 800mA main, ±500mA dual
Short circuit, any output
10% Load to/from 50% load
V
TL
8.0
100
150
275
mV
P-P
mA
P-P
KHz
%
W
ARM2812(dual)
ARM2815(dual)
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
±11.70
±14.50
3.0
150
±12.30
±15.15
30
3000
mA
W
Conditions unless otherwise specified
I
OUT
= 1.5 Adc
(main)
Group A
Subgroups
1, 2, 3
Min
4.95
Max
5.05
V
Units
I
OUT
= minimum rated, Pin 3 open
Input current
I
IN
Notes to Group A Test Table
1.
2.
3.
4.
5.
6.
7.
Parameter verified during dynamic load regulation tests
Guaranteed for DC to 20 MHz bandwidth. Test conducted using a 20KHz to 2MHz bandwidth.
Load current is stepped for output under test while other outputs are fixed at half rated load.
Each output is measured for all combinations of line and load. Only the minimum and maximum readings for each output are recorded.
Load step transition time
≥
10µS.
Recovery time is measured from the initiation of the transient to where V
OUT
has returned to within ±1% of its steady state value.
Turn on delay time is tested by application of a logical low to high transition on the enable pin (pin 3) with power present at the input.
8. Subgroups 1 and 4 are performed at +25°C, subgroups 2 and 5 at -55°C and subgroups 3 and 6 at +125°C
.
4
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ARM28XXT Series
Radiation Performance
The radiation tolerance characteristics inherent in the
ARM28XXT converter are based on the results of the
ground-up design effort on the ART2800T program and
started with specific radiation design goals. By imposing
sufficiently large margins on those electrical parameters
subject to the degrading effects of radiation, appropriate
elements were selected for incorporation into the
ART2800T circuit. Known radiation data was utilized for
input to PSPICE and RadSPICE in the generation of circuit
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