The AHV Series of DC/DC converters are designed to
replace the AHE/ATO family of converters in applications
requiring compliance to MIL-STD-704A through E, in
particular the input surge requirement of 80V specified to
withstand transient input voltage of 80V. No input voltage
or output power derating is necessary over the full military
temperature range.
These converters are packaged in an extremely rugged,
low profile package that meets all requirements of MIL-
STD-883 and MIL-PRF-38534. Parallel seam weld sealing
and the use of ceramic pin feed thru seals assure long
term hermeticity after exposure to extended temperature
cycling.
The basic circuit is a push-pull forward topology using
power MOSFET switches. The nominal switching
frequency is 500KHz. A unique current injection circuit
assures current balancing in the power switches. All AHV
series converters use a single stage LC input filter to
attenuate input ripple current. A low power 11.5V series
regulator provides power to an epitaxial CMOS custom
pulse width modulator integrated circuit. This single
integrated circuit provides all PWM primary circuit
functions. Power is transferred from primary to secondary
through a ferrite core power transformer. An error voltage
signal is generated by comparing a highly stable reference
voltage with the converter output voltage and drives the
PWM through a unique wideband magnetic feedback
circuit. This proprietary feedback circuit provides an
extremely wide bandwidth, high gain control loop, with
high phase margin. The feedback control loop gain is
insensitive to temperature, radiation, aging, and variations
in manufacturing. The transfer function of the feedback
circuit is a function of the feedback transformer turns ratio
which cannot change when subjected to environmental
extremes.
Manufactured in a facility fully qualified to MIL-PRF-38534,
these converters are fabricated utilizing DSCC qualified
processes. For available screening options, refer to device
screening table in the data sheet. Variations in electrical,
mechanical and screening can be accommodated.
Contact IR Santa Clara for special requirements.
28V Input, Single, Dual and Triple Output
AHV
Features
n
n
n
n
n
n
n
n
n
n
n
n
n
n
80V Transient Input (100 msec max.)
50V DC Input (Continous)
16V to 40V DC Input Range
Single, Dual and Triple Outputs
15W Output Power
(No Temperature Derating)
Low Input / Output Noise
Full Military Temperature Range
Wideband PWM Control Loop
Magnetic Feedback
Low Profile Hermetic Package (0.405”)
Short Circuit and Overload Protection
Constant Switching Frequency (500KHz)
True Hermetic Package (Parallel Seam
Welded, Ceramic Pin Feedthru)
Standard Microcircuit Drawings Available
www.irf.com
1
12/13/06
AHV28XX Series
T
CASE
= -55°C to +125°C, V
IN
= +28V
±
5% unless otherwise specified
Specifications (Single Output Models)
Absolute Maximum Ratings
Input voltage
Power output
Soldering temperature
Operating case temperature
Storage case temperature
Condition
-55°C
≤
T
C
≤
+125°C,
V
IN
= 28 V
DC
±5%,
C
L
=0,
unless otherwise specified
-0.5V to +50VDC (Continous), 80V (100 msec)
Internally limited, 17.5W typical
300°C for 10 seconds (1 pin at a time)
-55°C to +125°C
-65°C to +135°C
TEST
STATIC
CHARACTERISTICS
OUTPUT
Voltage
Current
Ripple Voltage
1
Power
REGULATION
Line
Load
INPUT
Current
Ripple Current
EFFICIENCY
ISOLATION
SYMBOL
Group A
Subgroups
AHV2805S
Min
Max
AHV2812S
Min
Max
AHV2815S
Min
Max
Units
V
OUT
I
OUT
V
RIP
P
OUT
VRLINE
VRLOAD
I
IN
I
RIP
E
FF
ISO
V
IN
= 16, 28, and 40 VDC
I
OUT
= 0
V
IN
= 16, 28, and 40 VDC
V
IN
= 16, 28, and 40 VDC
BW = DC to 1 MHz
V
IN
= 16, 28, and 40 VDC
V
IN
= 16, 28, and 40 VDC
I
OUT
= 0, half load and full load
VIN = 16, 28, and 40 VDC
I
OUT
= 0, half load and full load
I
OUT
= 0, Inhibit (pin 2) = 0
I
OUT
= 0, Inhibit (pin 2) = Open
I
OUT
= Full load
I
OUT
= Full Load
T
C
= +25°C
Input to output or any pin to
case (except pin 8) at 500
VDC
TC = +25°C
No effect on DC performance
TC = +25°C
Overload, TC = +25°C
Short Circuit, TC = +25°C
I
OUT
= Full Load
4
1
2,3
1,2,3
1,2,3
1,2,3
1
2,3
1,2,3
1,2,3
1,2,3,
1
1
4.95
4.90
0.0
15
5.05
5.10
3.00
60
11.88
11.76
0.0
15
12.12
12.24
1.25
60
14.85
14.70
0.0
15
15.15
15.30
1.00
60
V
V
A
mVp-p
W
5.0
25
50
18
50
50
72
100
72
100
30
60
120
18
50
50
72
100
35
75
150
18
50
50
mV
mA
mA
mAp-p
%
MΩ
Capacitive Load
2,3
Load Fault
Power Dissipation
Switching Frequency
DYNAMIC
CHARACTERISTICS
Step Load Changes
Output Transient
5
Recovery
5,6
C
L
P
D
F
S
4
1
500
8.5
8.5
450
550
450
200
8,5
8.5
550
450
200
8.5
8.5
550
µF
W
4
KHz
VOT
LOAD
TT
LOAD
50% Load
135
100% Load
No Load
135
50%
50% Load
135
100%
No Load
335
50% Load
50% Load
335
No lLoad
Input step 16 to 40 VDC
3,7
Input step 40 to 16 VDC
3,7
Input step 16 to 40 VDC
3,6,7
Input step 40 to 16 VDC
3,6,7
I
OUT
= OA and Full Load
I
OUT
= O and Full Load
8
V
IN
= 16 to 40 VDC
4
4
4
4
4
4
4
4
4
4,5,6
4,5,6
4,5,6
-300
-500
+300
+500
70
200
5.0
300
-1000
800
800
550
10
10
-300
-750
+300
+750
70
1500
5.0
500
-1500
800
800
750
10
10
-300
-750
+300
+750
70
1500
5.0
500
-1500
800
800
750
10
10
mVpk
mVpk
µs
µs
ms
mVpk
mVpk
µs
µs
mVpk
ms
ms
Step Line Changes
Output Transient
Recovery
TURN-ON
Overshoot
Delay
Load Fault Recovery
VOT
LINE
TT
LINE
VTon
os
T on D
TR
LF
Notes to Specifications (Single Output Models)
1. Bandwidth guaranteed by design. Tested for 20KHz to 2MHz.
2. Capacitive load may be any value from 0 to the maximum limit without affecting dc performance. A capacitive load in excess of the maximum limit will not disturb
loop stability but will interfere with the operation of the load fault detection circuitry, appearing as a short circuit during turn-on.
3. Parameter shall be tested as part of design characterization and after design or process changes. Thereafter shall be guaranteed to the limits specified.
4. An overload is that condition with a load in excess of the rated load but less than necessary to trigger the short circuit protection and is the condition of maximum
power dissipation.
5. Load step transition time between 2µs to 10µs.
6. Recovery time is measured from the initiation of the transient to where V
OUT
has returned to within
±1%
of V
OUT
at 50% load.
7. Input step transition time between 2µs and 10µs.
8. Turn on delay time measurement is for either a step application of power at input or the removal of a ground signal from the inhinbit pin (pin 2) while power is
applied to the input. Above 125°C case temperature, derate output power linearly to 0 at 135°C case.
2
www.irf.com
AHV28XX Series
Specifications (Dual Output Models)
T
CASE
= -55°C to +125°C, V
IN
= +28V
±
5% unless otherwise specified
Absolute Maximum Ratings
Input voltage
Power output
Soldering temperature
Operating case temperature
Storage case temperature
Condition
-55°C
≤
T
C
≤
+125°C,
V
IN
= 28 V
DC
±5%,
C
L
=0,
unless otherwise specified
-0.5V to +50VDC (Continous), 80V (100 msec)
Internally limited, 17.5W typical
300°C for 10 seconds (1 pin at a time)
-55°C to +125°C
-65°C to +135°C
TEST
STATIC
CHARACTERISTICS
OUTPUT
Voltage
1
Current
1,2
Ripple Voltage
1,3
Power
1,2,4
REGULATION
Line
1,5
Load
1
SYMBOL
Group A
Subgroups
AHV2805D
Min
Max
AHV2812
Min
Max
AHV281D
Min
Max
Units
V
OUT
I
OUT
V
RIP
P
OUT
VR
LINE
I
OUT
VR
LOAD
I
IN
I
RIP
E
FF
ISO
I
OUT
= 0
V
IN
= 16, 28, and 40 VDC
V
IN
= 16, 28, and 40 VDC
BW = DC to 2 MHz
V
IN
= 16, 28, and 40 VDC
V
IN
= 16, 28, and 40 VDC
I
OUT
= 0, half load and full load
VIN = 16, 28, and 40 VDC
I
OUT
= 0, half load and full load
I
OUT
= 0, Inhibit (pin 2)
Tied to input return (pin 10)
I
OUT
= 0, Inhibit (pin 2) = Open
I
OUT
= Full load
BW = DC to 2MHz
I
OUT
= Full Load
T
C
= +25°C
Input to output or any pin to
case (except pin 8) at 500 VDC,
TC = +25°C
No effect on DC performance
TC = +25°C
Overload, TC = +25°C
8
Short Circuit, TC = +25°C
I
OUT
= Full Load
1
2,3
1,2,3
1,2,3
1,2,3
1
2,3
1,2,3
1,2,3
1,2,3,
1
1
4
1
±4.95
±4.90
0.0
15
±5.05
±5.10
±1500
60
±11.88
±11.76
0.0
15
±12.12
±12.24
±625
60
±14.85
±14.70
0.0
15
±15.15
±15.30
±500
60
V
V
mA
mVp-p
W
30
60
120
18
65
50
72
100
200
8,5
8.5
450
550
450
72
100
30
60
120
18
65
50
72
100
200
8,5
8.5
550
450
35
75
150
18
65
50
mV
INPUT
Current
Ripple Current
3
EFFICIENCY
ISOLATION
Capacitive Load
6,7
mA
mA
mAp-p
%
MΩ
C
L
P
D
F
S
200
8.5
8.5
550
µF
W
Load Fault
Power Dissipation
Switching Frequency
4
KHz
DYNAMIC
CHARACTERISTICS
Step Load Changes
Output Transient
9
Recovery
9,10
VOT
LOAD
TT
LOAD
50% Load
135
100% Load
No Load
135
50%
50% Load
135
100%
No Load
335
50% Load
50% Load
335
No lLoad
Input step 16 to
Input step 40 to
Input step 16 to
Input step 40 to
40 VDC
16 VDC
40 VDC
16 VDC
4
4
4
4
4
4
4
4
4
4,5,6
4,5,6
4,5,6
-300
-500
+300
+500
70
200
5.0
300
1000
4800
4800
550
10
10
-300
-500
+300
+500
70
1500
5.0
1200
-1500
4.0
4.0
600
10
10
-300
-500
+300
+500
70
1500
5.0
1500
-1500
4.0
4.0
600
10
10
mVpk
mVpk
µs
µs
ms
mVpk
mVpk
µs
µs
mVpk
ms
ms
Step Line Changes
Output Transient
7,11
Recovery
7,10, 11
VOT
LINE
TT
LINE
VTon
OS
T on D
TR
LF
TURN-ON
Overshoot
1
Delay
1,12
Load Fault Recovery
7
I
OUT
= O and Full Load
I
OUT
= O and Full Load
For Notes to Specifications, refer to page 5
www.irf.com
3
AHV28XX Series
Specifications (Triple Output Models)
T
CASE
= -55°C to +125°C, V
IN
= +28V
±
5% unless otherwise specified
Absolute Maximum Ratings
Input voltage
Power output
Soldering temperature
Operating case temperature
Storage case temperature
Condition
-55°C
≤
T
C
≤
+125°C,
V
IN
= 28 V
DC
±5%,
C
L
=0,
unless otherwise specified
-0.5V to +50VDC (Continous), 80V (100 msec)
Internally limited, 17.5W typical
300°C for 10 seconds (1 pin at a time)
-55°C to +125°C
-65°C to +135°C
TEST
STATIC
CHARACTERISTICS
OUTPUT
Voltage
1
SYMBOL
Group A
Subgroups
AHV2812T
Min
Max
AHV2815T
Min
Max
Units
V
OUT
I
OUT
= 0 (main)
I
OUT
= 0 (dual)
1
Current
1,2,3
Ripple Voltage
1,4
I
OUT
V
RIP
Power
1,2,3
P
OUT
V
IN
= 16, 28, and 40 VDC (main)
V
IN
= 16, 28, and 40 VDC (dual)
1
V
IN
= 16, 28, and 40 VDC
BW = DC to 2 MHz (main)
V
IN
= 16, 28, and 40 VDC
BW = DC to 2 MHz (main)
V
IN
= 16, 28, and 40 VDC (main)
(+dual)
(-dual)
(total)
V
IN
= 16, 28, and 40 VDC
I
OUT
= 0, 50%, and 100% load (main)
I
OUT
= 0, 50%, and 100% load (dual)
V
IN
= 16, 28, and 40 VDC
I
OUT
= 0, 50%, and 100% load (main)
I
OUT
= 0, 50%, and 100% load (dual)
I
OUT
= 0, Inhibit (pin 8)
Tied to input return (pin 10)
I
OUT
= 0
Inhibit (pin 2) = open
I
OUT
= 2000 mA (main)
I
OUT
=
±208mA
(±12V)
I
OUT
=
±167mA
(±15V)
BW = DC to 2MHz
I
OUT
= 2000mA (main)
I
OUT
=
±
208mA (
±
12V)
I
OUT
=
±167mA
(±15V)
Input to output or any pin to
case (except pin 7) at 500 VDC,
TC = +25
°
C
No effect on DC performance
TC = +25°C (main)
(dual)
Overload, TC = +25°C
5
Short Circuit, TC = +25°C
I
OUT
= 2000mA (main)
I
OUT
=
±208mA
(±12V)
I
OUT
=
±167mA
(±15V)
1
2,3
1
2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
4.95
4.90
±
11.88
±11.76
0.0
0.0
5.05
5.10
±
12.12
±12.24
2000
±208
80
40
4.95
4.90
±
14.85
±14.70
0.0
0.0
5.05
5.10
±
15.15
±15.30
2000
±167
80
40
V
V
V
V
mA
mA
mVp-p
MVp-p
W
W
W
W
10
2.5
2.5
15
25
±
60
50
±60
10
2.5
2.5
15
25
±
75
50
±75
15
50
50
REGULATION
Line
1,3
Load
1,3
VR
LINE
VR
LOAD
mV
INPUT
Current
I
IN
1,2,3
1,2,3
1,2,3
15
50
50
mA
mA
mAp-p
Ripple Current
4
I
RIP
EFFICIENCY
E
FF
1
72
72
%
ISOLATION
Capacitive Load
6,7
Load Fault
Power Dissipation
3
Switching Frequency
1
ISO
C
L
1
100
100
MΩ
4
1
1
4
450
500
200
8.5
8.5
550
450
500
200
8.5
8.5
550
µF
W
P
D
F
S
KHz
For Notes to Specifications, refer to page 5
4
www.irf.com
AHV28XX Series
Specifications (Triple Output Models) - continued
Condition
-55°C
≤
T
C
≤
+125°C,
V
IN
= 28 V
DC
±5%,
C
L
=0,
unless otherwise specified
Group A
Subgroups
AHV2812T
Min
Max
AHV2815T
Min
Max
Units
TEST
DYNAMIC
CHARACTERISTICS
Step Load Changes
9
Output Transient
Recovery
9,10
SYMBOL
VOT
LOAD
TT
LOAD
50% Load
135
100% Load
No Load
135
50%
50% Load
135
100%
No Load
335
50% Load
50% Load
335
No lLoad
Input step 16 to 40 VDC
Input step 40 to 16 VDC
Input step 16 to 40 VDC
Input step 40 to 16 VDC
I
OUT
= o and
±625mA
I
OUT
= o and
±
625mA
4
4
4
4
4
4
4
4
4
4
4
4
-300
-400
+300
+400
100
2000
5.0
1200
-1500
4.0
4.0
750
15
15
-300
-400
+300
+400
100
2000
5.0
1200
-1500
4.0
4.0
750
15
15
mVpk
mVpk
µs
µs
ms
mVpk
mVpk
µ
s
µs
mVpk
ms
ms
Step Line Changes
Output Transient
Recovery
7,10, 11
VOT
LINE
TT
LINE
TURN-ON
Overshoot
1
1,12
Delay
7
Load Fault Recovery
VTon
OS
T on D
TR
LF
Notes to Specifications (Triple Output Models)
Tested at each output.
Parameter guaranteed by line and load regulation tests.
At least 25% of the total power should be taken from the (+5V) main output.
Bandwidth guaranteed by design. Tested for 20KHz to 2MHz.
An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit
protection and is the condition of maximum power dissipation.
6. Capacitive load may be any value from 0 to the maximum limit without affecting dc performance. A capacitive load in excess of the
maximum limit will not disturb loop stability but may interfere with the operation of the load fault detection circuitry, appearing as a
short circuit during turn-on.
7. Parameter shall be tested as part of design characterization and after design or process changes. Thereafter parameters shall be
guaranteed to the limits specified.
8. Above 125°C case temperature, derate output power linearly to 0 at 135°C case.
9. Load step transition time between 2
µs
and 10
µs
.
10. Recovery time is measured from the initiation of the transient to where V
OUT
has returned to within
±1%
of V
OUT
at 50% load.
11. Input step transition time between 2
µs
and 10
µs
.
12. Turn on delay time measurement is for either a step application of power at input or the removal of a ground signal from the inhibit
pin (pin 8) while power is applied to the input.
1.
2.
3.
4.
5.
Notes to Specifications (Dual Output Models)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Tested at each output.
Parameter guaranteed by line and load regulation tests.
Bandwidth guaranteed by design. Tested for 20KHz to 2MHz.
Total power at both outputs.
When operating with unbalanced loads, at least 25% of the load must be on the positive output to maintain regulation.
Capacitive load may be any value from 0 to the maximum limit without affecting dc performance. A capacitive load in excess of the
maximum limit will not disturb loop stability but may interfere with the operation of the load fault detection circuitry, appearing as a
short circuit during turn-on.
Parameter shall be tested as part of design characterization and after design or process changes. Thereafter parameters shall be
guaranteed to the limits specified.
An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit
protection and is the condition of maximum power dissipation.
Load step transition time between 2
µs
and 10
µs
.
Recovery time is measured from the initiation of the transient to where V
OUT
has returned to within
±1%
of V
OUT
at 50% load.
Input step transition time between 2
µs
and 10
µs
.
Turn on delay time measurement is for either a step application of power at input or the removal of a ground signal from the inhibit
pin (pin 2) while power is applied to the input.
Above 125°C case temperature, derate output power linearly to 0 at 135°C.
这标志着在物流供应链打印中处于全球领先地位的美国普印力PRINTRONIX更加看好中国市场，进一步加大在中国的投资力度，依托国际性分销商和本土的行业巨头进一步深入中国市场。 来自政府相关部门的领导、自动识别行业专家、行业客户代表以及新闻媒体出席了新闻发布会，普印力全球高级销售总裁James B. McWilson以及大中华区总经理Roger Zhao出席会议，与闪联总裁孙育宁博士现场...[详细]
卡巴斯基的安全研究人员称其发现了如何攻击Intel微处理器的远程攻击代码，据传，这一代码可以通过TCP/IP包和JavaScript代码到达用户系统。 目前受影响的系统包括Windows XP，Vista，Windows Server 2003，Windows Server 2008，Linux甚至是BSD和Mac。但所幸大多数错误可以由Intel和BIOS厂商联合进行修复。 卡...[详细]
Yamaha Motor Group旗下的i-PULSE有限公司日前已与华尔莱科技（Valor）结为合作伙伴关系，基于Valor的vPlan生产规划工具向i-PULSE组装设备的使用者提供完整的从设计到制造的NPI解决方案。在近期日本东京举办的Protec展会（6/11-6/13）上，i-PULSE首度展出了该新产品并将直接向其客户进行销售。 新产品的名称为“iPlan”，它将提供一系...[详细]
2008年7月17～18日，由深圳创意时代主办的“第四届便携式产品设计与电源管理技术研讨会”在深圳隆重召开。为期两天的大会紧紧围绕便携产品设计、便携电源管理两大主题展开，引起了关于便携主题的广泛讨论。国际知名企业TI、ST 、ADI倾情参与，知名行业分析机构IN-Stat China 预测了行业的最新趋势，3M、飞兆、英飞凌、精工、爱国者、中电等国内外著名企业都发表了精彩演讲。 精彩的...[详细]
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
