IDT74FCT16543AT/CT
FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
16-BIT LATCHED
TRANSCEIVER
FEATURES:
DESCRIPTION:
IDT74FCT16543AT/CT
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
≤
1µA (max.)
V
CC
= 5V ±10%
High drive outputs (–32mA I
OH
, 64mA I
OL
)
Power off disable outputs permit “live insertion”
Typical V
OLP
(Output Ground Bounce) < 1.0V at V
CC
= 5V,
T
A
= 25°C
• Available in SSOP and TSSOP packages
The FCT16543T 16-bit latched transceivers are built using advanced
dual metal CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type latched transceivers with
separate input and output control to permit independent control of data flow
in either direction. For example, the A-to-B Enable (xCEAB) must be low
in order to enter data from the A port or to output data from the B port. xLEAB
controls the latch function. When xLEAB is low, the latches are transparent.
A subsequent low-to-high transition of xLEAB signal puts the A latches in
the storage mode. xOEAB performs output enable function on the B port.
Data flow from the B port to the A port is similar but requires using xCEBA,
xLEBA, and xOEBA inputs. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
The FCT16543T is ideally suited for driving high-capacitance loads
and low-impedance backplanes. The output buffers are designed with
power off disable capability to allow "live insertion" of boards when used
as backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
1
OEBA
56
2
OEBA
29
1
CEBA
54
1
LEBA
1
OEAB
1
CEAB
1
LEAB
55
1
3
2
2
CEBA
31
2
LEBA
2
OEAB
2
CEAB
2
LEAB
30
28
26
27
C
1
A
1
5
2
A
1
15
C
D
C
D
42
D
C
D
52
1
B
1
2
B
1
TO SEVEN OTHER CHANNELS
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
TO SEVEN OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
©2017
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2017
1
DSC-5444/6
IDT74FCT16543AT/CT
FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OEAB
1
LEAB
1
CEAB
PIN DESCRIPTION
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
1
LEBA
1
CEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
1
A
1
1
A
2
GND
1
B
1
1
B
2
Pin Names
xOEAB
xOEBA
xCEAB
xCEBA
xLEAB
xLEBA
xAx
xBx
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
V
CC
1
A
3
1
A
4
1
A
5
V
CC
1
B
3
1
B
4
1
B
5
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to 7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Outputs and I/O terminals for FCT162XXX.
GND
2
A
4
2
A
5
2
A
6
GND
2
B
4
2
B
5
2
B
6
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
V
CC
2
A
7
2
A
8
V
CC
2
B
7
2
B
8
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE
(1, 2)
For A-to-B (Symmetric with B-to-A)
Inputs
xLEAB
X
H
L
H
L
H
Latch
Status
xAx to xBx
Storing
Storing
Transparent
Storing
Transparent
Storing
Output
Buffers
xBx
Z
X
Current A Inputs
Previous* A Inputs
Z
Z
GND
2
CEAB
2
LEAB
2
OEAB
GND
2
CEBA
2
LEBA
2
OEBA
TOP VIEW
Package Type
TSSOP
SSOP
Package Code
PAG56
PVG56
Order Code
PAG
PVG
xCEAB
H
X
L
L
L
L
xOEAB
X
X
L
L
H
H
NOTES:
1. * Before xLEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. A-to-B data flow shown; B-to-A flow control is the same, except using xCEBA, xLEBA
and xOEBA.
2
IDT74FCT16543AT/CT
FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max
V
IN
= GND or V
CC
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
=
GND
(3)
—
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
V
I
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
Min.
2
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
0.8
±1
±1
±1
±1
±1
±1
–1.2
–250
—
500
V
mA
mV
µA
µA
Unit
V
V
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
O
V
OH
Parameter
Output Drive Current
Output HIGH Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
OL
I
OFF
Output LOW Voltage
Input/Output Power Off Leakage
(5)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
= or V
O
≤
4.5V
—
—
±1
μA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is ±5µA at T
A
= –55°C.
Test Conditions
(1)
V
CC
= Max.
,
V
O
= 2.5V
(3)
I
OH
= –3mA
I
OH
= –15mA
I
OH
= –32mA
(4)
I
OL
= 64mA
Min.
–50
2.5
2.4
2
—
Typ.
(2)
—
3.5
3.5
3
0.2
Max.
–180
—
—
—
0.55
Unit
mA
V
V
V
V
3
IDT74FCT16543AT/CT
FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max., Outputs Open
xCEAB and xOEAB = GND
xCEBA = V
CC
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
i
= 10MHz
50% Duty Cycle
xLEAB, xCEAB and
xOEAB = GND
xCEBA = V
CC
One Bit Toggling
V
CC
= Max., Outputs Open
f
i
= 2.5MHz
50% Duty Cycle
xLEAB, xCEAB and
xOEAB = GND
xCEBA = V
CC
Sixteen Bits Toggling
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
60
Max.
1.5
100
Unit
mA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
0.6
1.5
mA
—
0.9
2.3
—
2.4
4.5
(5)
—
6.4
16.5
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
4
IDT74FCT16543AT/CT
FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
SU
t
H
t
W
t
SK(o)
Parameter
Propagation Delay
Transparent Mode
xAx to xBx or xBx to xAx
Propagation Delay
xLEBA to xAx, xLEAB to xBx
Output Enable Time
xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
Output Disable Time
xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
Set-up Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
Hold Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
xLEAB or xLEBA Pulse Width LOW
Output Skew
(3)
Condition
(2)
C
L
= 50pF
R
L
= 500Ω
74FCT16543AT
Min.
(2)
Max.
1.5
6.5
74FCT16543CT
Min.
(2)
Max.
1.5
5.1
Unit
ns
1.5
1.5
8
9
1.5
1.5
5.6
7.8
ns
ns
1.5
7.5
1.5
6.5
ns
2
2
4
—
—
—
—
0.5
2
2
4
—
—
—
—
0.5
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
下载中心专版
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
