SiHP14N50D
www.vishay.com
Vishay Siliconix
D Series Power MOSFET
PRODUCT SUMMARY
V
DS
(V) at T
J
max.
R
DS(on)
max. at 25 °C ()
Q
g
max. (nC)
Q
gs
(nC)
Q
gd
(nC)
Configuration
V
GS
= 10 V
58
8
14
Single
550
0.4
FEATURES
• Optimal Design
- Low Area specific On-Resistance
- Low Input Capacitance (C
iss
)
- Reduced Capacitive Switching Losses
- High Body Diode Ruggedness
- Avalanche Energy Rated (U
IS
)
• Optimal Efficiency and Operation
- Low Cost
- Simple Gate Drive Circuitry
- Low Figure-Of-Merit (FOM): R
on
x Q
g
- Fast Switching
• Material categorization: For definitions of compliance
please see
www.vishay.com/doc?99912
Note
*
Lead (Pb)-containing terminations are not RoHS-compliant.
Exemptions may apply.
S
N-Channel MOSFET
TO-220AB
D
G
D
S
G
APPLICATIONS
• Consumer Electronics
- Displays (LCD or Plasma TV
• Server and Telecom Power Supplies
- SMPS
• Industrial
- Welding, Induction Heating, Motor Drives
• Battery Chargers
ORDERING INFORMATION
Package
Lead (Pb)-free
Lead (Pb)-free and Halogen-free
TO-220AB
SiHP14N50D-E3
SiHP14N50D-GE3
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Gate-Source Voltage AC (f > 1 Hz)
Continuous Drain Current (T
J
= 150 °C)
Pulsed Drain
Current
a
Energy
b
V
GS
at 10 V
T
C
= 25 °C
T
C
= 100 °C
SYMBOL
V
DS
V
GS
I
D
I
DM
E
AS
P
D
T
J
, T
stg
T
J
= 125 °C
dV/dt
LIMIT
500
± 30
30
14
9
38
1.6
56
208
- 55 to + 150
24
0.4
300
c
W/°C
mJ
W
°C
V/ns
°C
A
V
UNIT
Linear Derating Factor
Single Pulse Avalanche
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
Reverse Diode dV/dt
d
Soldering Recommendations (Peak Temperature)
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. V
DD
= 50 V, starting T
J
= 25 °C, L = 2.3 mH, R
g
= 25
,
I
AS
= 7 A.
c. 1.6 mm from case.
d. I
SD
I
D
, starting T
J
= 25 °C.
S12-1229-Rev. A, 21-May-12
Document Number: 91512
1
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHP14N50D
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
Maximum Junction-to-Case (Drain)
SYMBOL
R
thJA
R
thJC
TYP.
-
-
MAX.
62
0.6
UNIT
°C/W
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
Gate Threshold Voltage (N)
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
a
Dynamic
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance, Energy
Related
a
Effective Output Capacitance, Time
Related
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Gate Input Resistance
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
T
J
= 25 °C, I
F
= I
S
= 7 A,
dI/dt = 100 A/μs, V
R
= 20 V
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
C
o(er)
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 250 μA
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= ± 30 V
V
DS
= 500 V, V
GS
= 0 V
V
DS
= 400 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 7 A
V
DS
= 50 V, I
D
= 7 A
500
-
3.0
-
-
-
-
-
-
-
-
-
-
0.58
-
-
-
-
0.320
5.2
1144
100
12
87
125
29
8
14
16
27
29
26
1.7
-
-
5.0
± 100
1
10
0.40
-
-
-
-
V
V/°C
V
nA
μA
S
V
GS
= 0 V,
V
DS
= 100 V,
f = 1 MHz
pF
-
-
58
-
-
32
54
58
52
-
ns
nC
V
GS
= 0 V, V
DS
= 0 V to 480 V
C
o(tr)
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
R
g
f = 1 MHz, open drain
V
DD
= 400 V, I
D
= 7 A,
V
GS
= 10 V, R
g
= 9.1
V
GS
= 10 V
I
D
= 7 A, V
DS
= 400 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
319
3.0
18
14
A
56
1.2
-
-
-
V
ns
μC
A
G
S
T
J
= 25 °C, I
S
= 7 A, V
GS
= 0 V
Notes
a. C
oss(er)
is a fixed capacitance that gives the same energy as C
oss
while V
DS
is rising from 0 % to 80 % V
DSS
.
b. C
oss(tr)
is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 % to 80 % V
DSS
.
S12-1229-Rev. A, 21-May-12
Document Number: 91512
2
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHP14N50D
www.vishay.com
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Vishay Siliconix
40
3
I
D
, Drain-to-Source Current (A)
R
DS(on)
, Drain-to-Source
On Resistance (Normalized)
30
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
T
J
= 25 °C
2.5
2
1.5
1
0.5
I
D
= 7 A
20
V
GS
= 10 V
10
0
0
5
10
15
5.0 V
20
25
30
0
- 60 - 40 - 20 0
20 40 60 80 100 120 140 160
V
DS
, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
T
J
, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
30
I
D
, Drain-to-Source Current (A)
24
Capacitance (pF)
18
15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
BOTYTOM 5.0 V
TOP
10 000
T
J
= 150 °C
C
iss
1000
V
GS
= 0 V, f = 1 MHz
C
iss
= C
gs
+ C
gd
, C
ds
Shorted
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
C
oss
10
C
rss
100
12
6
5.0 V
0
0
5
10
15
20
25
30
1
0
100
200
300
400
500
V
DS
, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
V
DS
, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
40
24
V
GS
,
Gate-to-Source
Voltage (V)
I
D
, Drain-to-Source Current (A)
20
16
12
8
4
0
V
DS
= 400 V
V
DS
= 250 V
V
DS
= 100 V
30
20
10
T
J
= 150 °C
T
J
= 25 °C
0
0
5
10
15
20
25
0
10
20
30
40
50
V
GS
, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S12-1229-Rev. A, 21-May-12
Q
g
, Total
Gate
Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91512
3
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHP14N50D
www.vishay.com
Vishay Siliconix
100
16
I
SD
, Reverse Drain Current (A)
I
D
, Drain Current (A)
V
GS
= 0 V
1.2
1.4
1.6
12
10
T
J
= 150 °C
8
1
T
J
= 25 °C
4
0.1
0.2
0.4
0.6
0.8
1
0
25
50
75
100
125
150
V
SD
,
Source-Drain
Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
T
J
, Case Temperature (°C)
Fig. 9 - Maximum Drain Current vs. Case Temperature
1000
625
600
I
DM
= Limited
100
I
D
, Drain Current (A)
V
DS
, Drain-to-Source
Brakdown Voltage (V)
Operation in this Area
Limited by R
DS(on)
575
550
525
500
475
- 60 - 40 - 20 0
10
Limited by R
DS(on)
*
100 μs
1 ms
1
T
C
= 25 °C
T
J
= 150 °C
Single
Pulse
1
10 ms
BVDSS Limited
1000
0.1
10
100
V
DS
, Drain-to-Source Voltage (V)
* V
GS
> minimum V
GS
at which R
DS(on)
is
s
20 40 60 80 100 120 140 160
T
J
, Junction Temperature (°C)
Fig. 10 - Temperature vs. Drain-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
Single
Pulse
0.01
0.0001
0.1
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
S12-1229-Rev. A, 21-May-12
Document Number: 91512
4
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHP14N50D
www.vishay.com
Vishay Siliconix
R
D
10 V
Q
G
V
DS
V
GS
R
G
D.U.T.
+
-
V
DD
Q
GS
Q
GD
10 V
Pulse width ≤ 1 μs
Duty factor ≤ 0.1 %
V
G
Fig. 12 - Switching Time Test Circuit
Charge
Fig. 16 - Basic Gate Charge Waveform
Current regulator
Same
type as D.U.T.
50 kΩ
12 V
V
DS
90 %
0.2 μF
0.3 μF
+
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
V
GS
3 mA
D.U.T.
-
V
DS
Fig. 13 - Switching Time Waveforms
I
G
I
D
Current
sampling
resistors
L
Vary t
p
to obtain
required I
AS
R
G
V
DS
Fig. 17 - Gate Charge Test Circuit
D.U.T.
I
AS
+
-
V
DD
10 V
t
p
0.01
Ω
Fig. 14 - Unclamped Inductive Test Circuit
V
DS
t
p
V
DD
V
DS
I
AS
Fig. 15 - Unclamped Inductive Waveforms
S12-1229-Rev. A, 21-May-12
Document Number: 91512
5
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
