HI-8450, HI-8451, HI-8454, HI-8455
January 2014
Single / Quad ARINC 429 Line Receivers with
Integrated DO-160G Level 3 Lightning Protection
•
Test inputs bypass analog inputs and force digital
outputs to a one, zero, or null state (not available
on HI-8455)
•
Industrial and Extended temperature ranges
•
Burn-in available
GENERAL DESCRIPTION
Holt’s family of ARINC 429 line receivers include internal
lightning protection circuitry which ensures compliance
with RTCA/DO-160G, Section 22 Level 3 Pin Injection
Test Waveform Set A (3 & 4), Set B (3 & 5A) and Set Z (3
& 5B) without the use of any external components. Pin
surge levels for Level 3 are summarized below. The HI-
8450 and HI-8451 are single ARINC 429 line receivers
available in compact 8-pin SOIC packages. The HI-8454
and HI-8455 contain 4 independent ARINC 429 line
receivers.
Waveform
3
VOC/ISC
600V/24A
Waveform
4
VOC/ISC
300V/60A
Waveform
5A
VOC/ISC
300V/300A
Waveform
5B
VOC/ISC
300V/300A
PIN CONFIGURATION (TOP VIEW)
VDD
TESTA
INB
INA
1
2
3
4
HI-8450PSx
HI-8451PSx
8
TESTB
7
OUTB
6
OUTA
5
GND
8-PIN PLASTIC SOIC - NB
The devices are designed to operate from either a 5V or
3.3V supply. Each receiver channel translates incoming
ARINC 429 data bus signals to a pair of TTL / CMOS
outputs.
The TESTA and TESTB inputs bypass the analog inputs
for testing purposes. They force the receiver outputs to
the specified ZERO, ONE or NULL state. The ARINC
inputs are ignored when the devices are in test mode.
The HI-8451 and HI-8454 produce low outputs when
the TESTA and TESTB inputs are held high, whereas
the HI-8450 produces high impedance outputs when
the TESTA and TESTB inputs are held high. The HI-
8455 does not have TEST inputs and these pins may be
considered no-connect (NC).
The parts are available in Industrial -40 C to +85 C, or
o
o
Extended, -55 C to +125 C temperature ranges. Optional
burn-in is available on the extended temperature range.
o
o
IN1A
IN1B
IN2A
IN2B
TESTA (8454 only)
TESTB (8454 only)
IN3A
IN3B
IN4A
IN4B
1
2
3
4
5
6
7
8
9
10
20
HI-8454PSx
&
HI-8455PSx
Quad
Receiver
19
18
17
16
15
14
13
12
11
OUT1A
OUT1B
OUT2A
OUT2B
VDD
GND
OUT3A
OUT3B
OUT4A
OUT4B
20-PIN PLASTIC TSSOP PACKAGE
Table 1. Function Table
ARINC
INPUTS
INA - INB
-2.5 to +2.5V
< -6.5V
> +6.5V
x
x
x
x
TESTA
TESTB
OUTA
OUTB
0
0
0
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
1
0
(1)
HI-Z
(2)
0
1
0
1
0
0
(1)
HI-Z
(2)
FEATURES
•
Internal lightning protection circuitry ensures
compliance with RTCA/DO-160G, Section 22
Level 3 Pin Injection Test Waveform Set A (3 &
4), Set B (3 & 5A) and Set Z (3 & 5B)
•
Direct connection to ARINC 429 bus with no
external components
•
3.3V or 5.0V single supply operation
Note (1): HI-8451 and HI-8454 only.
Note (2): HI-8450 only.
DS8450 Rev. New.
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
01/14
HI-8450, HI-8451, HI-8454, HI-8455
FUNCTIONAL DESCRIPTION
Figure 1 shows the general architecture of an ARINC 429
receiver. The receiver operates off the VDD supply only.
The inputs RINA and RINB may be connected directly to
the ARINC 429 bus. Internal lightning protection circuitry
ensures compliance with RTCA/DO-160G, Section 22
Level 3 Pin Injection Test Waveform Set A (3 & 4), Set
B (3 & 5A) and Set Z (3 & 5B) without the use of any
external components.
After level translation, the inputs are buffered and
become inputs to a differential amplifier. The amplitude
of the differential signal is compared to levels derived
from a divider between VDD and Ground. The nominal
settings correspond to a One/Zero amplitude of 6.0V
and a Null amplitude of 3.3V.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins (not available on HI-8455). If TESTA and
TESTB are both One, the outputs are pulled low (HI-
8451 and HI-8454 only). This allows the digital outputs
of a transmitter to be connected to the test inputs
through control logic for system self-test purposes. In
the case of HI-8450, if TESTA and TESTB are both One,
the outputs are high impedance (HI-Z).
BLOCK DIAGRAMS
ONE
S
R
Q
ROUTA
TESTA
TESTB
RINA
LIGHTNING
PROTECTION
AND
TRANSLATION
TEST
LATCH
NULL
TEST
RINB
ZERO
S
R
Q
LATCH
ROUTB
TESTA
TESTB
NULL
Figure 1. Line Receiver Block Diagram
IN1A
IN1B
IN2A
IN2B
IN3A
IN3B
IN4A
IN4B
TESTA
TESTB
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
Figure 2. HI-8454 Block Diagram
HOLT INTEGRATED CIRCUITS
2
HI-8450, HI-8451, HI-8454, HI-8455
PIN DESCRIPTIONS
Table 2. Pin Descriptions
Symbol
IN1A
IN1B
IN2A
IN2B
TESTA
TESTB
IN3A
IN3B
IN4A
IN4B
OUT4B
OUT4A
OUT3B
OUT3A
GND
VDD
OUT2B
OUT2A
OUT1B
OUT1A
Function
ARINC INPUT
ARINC INPUT
ARINC INPUT
ARINC INPUT
LOGIC INPUT
LOGIC INPUT
ARINC INPUT
ARINC INPUT
ARINC INPUT
ARINC INPUT
LOGIC OUTPUT
LOGIC OUTPUT
LOGIC OUTPUT
LOGIC OUTPUT
POWER
POWER
LOGIC OUTPUT
LOGIC OUTPUT
LOGIC OUTPUT
LOGIC OUTPUT
Description
Receiver 1 positive input
Receiver 1 negative input
Receiver 2 positive input
Receiver 2 negative input
Test input (not available on HI-8455)
Test input (not available on HI-8455)
Receiver 3 positive input
Receiver 3 negative input
Receiver 4 positive input
Receiver 4 negative input
Receiver 4 “ZERO” output
Receiver 4 “ONE” output
Receiver 3 “ZERO” output
Receiver 3 “ONE” output
Ground supply voltage
+3.3V or +5V supply voltage
Receiver 2 “ZERO” output
Receiver 2 “ONE” output
Receiver 1 “ZERO” output
Receiver 1 “ONE” output
HOLT INTEGRATED CIRCUITS
3
HI-8450, HI-8451, HI-8454, HI-8455
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V
DD
)
ARINC input voltage
-0.3V to +7V
-0.3V to +5.5V
-120V to + 120V
350mW
-65 C to +150 C
2,000V
1,000V
o
RECOMMENDED OPERATING
CONDITIONS
Supply Voltages
Temperature Range
V
DD
................................... 3.0V to +5.5V
Industrial Screening .............. -40 C to +85 C
Hi-Temp Screening .............. -55 C to +125 C
NOTE: Stresses above absolute maximum ratings or outside
recommended operating conditions may cause permanent damage to
the device. These are stress ratings only. Operation at the limits is not
recommended.
o
o
o
o
Logic input voltage range
Power dissipation at 25 C
Solder Temperature (reflow)
Storage Temperature
ESD-HBM (JS-001-2012)
Logic and supply pins
ARINC 429 bus input pins
o
260 C
o
o
RTCA/DO-160G, Section 22 pin injection
Waveform
3
4
5A
5B
Voc/Isc
1,000V/40A
500V/100A
500V/500A
500V/500A
ELECTRICAL CHARACTERISTICS
Table 3. DC Electrical Characteristics
V
DD
= +5.0V ± 10% or +3.3V ± 10%, GND = 0V, T
A
= Operating Temperature Range (unless otherwise stated)
Parameters
ARINC INPUTS
Input Voltage
ONE or ZERO
NULL
Common mode
Input Resistance
INA to INB
Input to GND or V
DD
Input Hysteresis
Input Capacitance
ARINC differential
ARINC single ended
to GND
Symbol
Test Conditions
Min
Typ
Max
Units
V
DIN
V
NIN
V
COM
R
DIFF
R
SUP
V
HYS
C
AD
C
AS
Differential Input voltage
Differential Input voltage
With respect to GND
Supplies floating
Supplies floating
6.5
10
13
2.5
±5.0
V
V
V
kΩ
kΩ
30
15
0.5
1.0
5
10
10
V
pF
pF
HOLT INTEGRATED CIRCUITS
4
HI-8450, HI-8451, HI-8454, HI-8455
Parameters
TEST INPUTS
Logic Input Voltage
High
Low
Logic Input Current
Sink
Source
OUTPUTS
Logic Output Voltage
High
V
OH
I
OH
= -5.0mA, V
DD
= 5.0V
I
OH
= -4.0mA, V
DD
= 3.3V
I
OH
= 5.0mA, V
DD
= 5.0V
I
OH
= 4.0mA, V
DD
= 3.3V
I
OH
= -100μA
I
OL
= 100μA
V
DD
−0.2
GND+0.2
2.4
2.4
0.4
0.5
V
V
V
V
V
V
IH
V
IL
I
IH
I
IL
V
IH
= V
DD
V
IL
= 0V
-1.0
80%V
DD
20%V
DD
200
V
V
μA
μA
Symbol
Test Conditions
Min
Typ
Max
Units
Low
Logic Output Voltage
(CMOS)
High
Low
SUPPLY CURRENT
V
DD
Current
(HI-8454)
V
OL
V
OHC
V
OLC
I
DD
V
DD
= 5.0V
V
DD
= 3.3V
V
DD
= 5.0V
V
DD
= 3.3V
14
9
12
8
20
15
18
14
mA
mA
mA
mA
V
DD
Current
(HI-8450, HI-8451)
I
DD
Table 4. AC Electrical Characteristics
V
DD
= +5.0V ± 10% or +3.3V ± 10%, GND = 0V, T
A
= Operating Temperature Range (unless otherwise stated)
Parameters
SWITCHING CHARACTERISTICS
Propagation Delay
IN to OUT
Symbol
Test Conditions
Min
Typ
Max
Units
t
LH
t
HL
C
L
= 50pF
C
L
= 50pF
10% to 90%
90% to 10%
150
150
15
15
50
50
300
300
50
50
ns
ns
ns
ns
ns
ns
Output Rise Time
Output Fall Time
Propagation Delay
TEST to OUT
t
R
t
F
t
TOH
t
TOL
HOLT INTEGRATED CIRCUITS
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