HI-8428
October 2015
8-Channel Ground/Open or Supply/Open
Sensor with SPI Interface
FEATURES
·
Robust CMOS Silicon-on-Insulator (SOI) technology
·
Eight discrete inputs, individually configurable as
GENERAL DESCRIPTION
The HI-8428 is an 8-channel discrete-to-digital sensor
fabricated with Silicon-on-Insulator (SOI) technology
designed to interface with a Serial Peripheral Interface
(SPI).
Each input is individually configurable as either GND/Open
or Supply/Open (28V/Open). Discrete input thresholds and
hysteresis are compliant with Airbus ADB0100H
specification. In GND/Open mode, thresholds are set at
4.5V/10.5V, and in Supply/Open mode at 6V/12V.
The part operates from a 3.3V (+/- 5%) digital supply and
12V - 16.5V analog supply.
A 1mA wetting current is sourced from each SENSE input
when GND/Open mode is selected for that pin. The wetting
current serves to prevent dry relay or switch contacts.
All sense inputs are internally lightning protected to
RTCA/DO160G, Section 22 Level 3 Pin Injection Test
Waveform Set A(3 & 4), Set B (3 & 5A) and Set Z (3 & 5B)
without the use of any external components.
HI-8428 is a drop-in replacement for the DEI1282.
GND/Open or Supply/Open
·
Airbus ABD0100H specification compliant
·
MIL-STD-704 compliant
·
Sense inputs lightning protected to RTCA/DO1060G,
·
·
·
·
Section 22 Level 3
10MHz Serial Peripheral Interface (SPI) allows daisy-
chaining of parts for efficient board routing
Withstands inadvertent application of 115V AC/400Hz
power to Sense inputs.
Internal Self-Test mode checks analog comparators
and logic
Drop-in replacement for DEI1282
PIN CONFIGURATION
SENSE1 1
SENSE2 2
SENSE3 3
SENSE4 4
SENSE5 5
SENSE6 6
SENSE7 7
SENSE8 8
HI-8428PSx
16 VDD
15 GND
14 VLOGIC
13 SEL
12 SI
11 CS
10 SCK
9 SO
APPLICATION
·
Avionics Discrete to Digital Sensing
16-Pin Plastic Small Outline
Narrow-body Package
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS8428 Rev. A)
10/15
HI-8428
BLOCK DIAGRAM
VLOGIC
VDD
SEL
CS
SCK
SPI
CONTROL
SI
DATA REGISTER
MUX
SHIFT REGISTER
SO
CONFIG REGISTER
CR1 (PSEN1)
CR2 (PSEN2)
CR3 (PSEN3)
CR4 (PSEN4)
CR5 (PSEN5)
CR6 (PSEN6)
CR7 (PSEN7)
CR8 (PSEN8)
CR9 (TEST)
POR
THRESHOLDS
PU
PD
HI LO HI LO
VREF
TEST
V
DD
SENSE
CONTROL
SW1
VTHI
CRn
VDD
2kΩ
10kΩ
680kΩ
20kΩ
LIGHTNING
PROTECTION
SW2
+
-
+
-
VTLO
SENSE1-8
SENSOR 1
SENSOR 2
SENSOR 3
SENSOR 4
SENSOR 5
SENSOR 6
SENSOR 7
SENSOR 8
GND
Figure 1.
HOLT INTEGRATED CIRCUITS
2
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
HI-8428
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SYMBOL
SENSE1
SENSE2
SENSE3
SENSE4
SENSE5
SENSE6
SENSE7
SENSE8
SO
SCK
CS
SI
SEL
VLOGIC
GND
VDD
FUNCTION
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Digital Output
Logic Input
Logic Input
Logic Input
Logic Input
Supply
Supply
Supply
DESCRIPTION
Sense input 1. Mapped to last (eighth) SPI bit shifted out of SO during data read
Sense input 2. Mapped to seventh SPI bit shifted out of SO during data read
Sense input 3. Mapped to sixth SPI bit shifted out of SO during data read
Sense input 4. Mapped to fifth SPI bit shifted out of SO during data read
Sense input 5. Mapped to fourth SPI bit shifted out of SO during data read
Sense input 6. Mapped to third SPI bit shifted out of SO during data read
Sense input 7. Mapped to second SPI bit shifted out of SO during data read
Sense input 8. Mapped to first SPI bit shifted out of SO during data read
SPI Data out
SPI clock input. 10MHz maximum clock frequency.
Chip Select. SPI data transfers are enabled when CS is low
SPI Data input.
Register Select. SEL high selects Data register. SEL low, selects Configuration register
Logic supply voltage. 3.3V +/- 5%
Ground
Analog Supply voltage 12V to 16.5V
HOLT INTEGRATED CIRCUITS
3
HI-8428
FUNCTIONAL DESCRIPTION
OVERVIEW
The HI-8428 is comprised of 8 sensors, which may be
individually configured for GND/Open or Supply/Open (also
known as 28V/Open) sensing. Eight bits of the on-chip
Configuration Register are used to set the sensor
configuration. A one in the Configuration Register selects
GND/Open and a zero selects Supply/Open mode. A ninth
bit in the Configuration Register is used to enable the chip’s
Built-In-Test (BIT) feature. The logical output from each
sensor is latched into an eight-bit Data Register on the
falling edge of the CS input.
Reading from and writing to the Configuration Register and
Data Register is accomplished using a serial interface
compatible with the industry-standard Serial Peripheral
Interface (SPI) bus.
Figure 1 shows a simplified block diagram of the HI-8428.
DATA REGISTER
AT
A8
AT
A
D
7
AT
D
A6
AT
A
D 5
AT
A
D 4
AT
D
A3
AT
D A2
AT
A1
D
8
D
7
6
5
4
3
2
1
First Bit shifted out of SO
Last Bit shifted out of SO
The eight-bit Data Register captures the output state from
the eight discrete sensors. Data is latched on the falling
edge of CS. The Data bits are read out from the chip over
the serial interface. Sensor 8 data bit is output first at SO
followed by the remaining seven sensor states. In either
mode (GND/Open or Supply/Open), a logic one is output
when the voltage at the sensor pin input is greater than
the high threshold and a logic zero is output when the
sensor voltage is lower than the low threshold, (see table
1).
Multiple HI-8428s may be daisy-chained together to allow
a single SPI read sequence to program configuration or
capture data from several ICs in one operation.
RESET AND INITIALIZATION
The HI-8428 includes an on-chip Power-On Reset (POR)
circuit, which forces the SENSE inputs to a high-impedance
state at power-up. Switches SW1 and SW2 (see Figure 1)
are open. The inputs remain high-impedance until the
Configuration Register is programmed, defining the
GND/Open (SW1 closed / SW2 open), or Supply/Open
(SW1 open / SW2 closed) for each sensor.
The HI-8428 registers are designed to retain programmed
logic states through VLOGIC power dips down to 1.5V
ensuring reliable operation in noisy environments without
the need to re-initialize the part.
SENSEn
Open or > 10.5V
< 4.5V
Open or < 7.5
> 12V
1
1
CRn
(GND/Open)
(GND/Open)
DRn
1
0
0
1
I
SENSE
1 mA
0 (Supply/Open)
0 (Supply/Open)
CONFIGURATION REGISTER
EN
R AB
8
LE
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
Table 1. Function Table
T
GND/OPEN SENSING
For GND/Open sensing, the CRn bit is set to 1. Referring
to the Block Diagram, Figure 1, this selection will connect a
12kΩ pull-up resistance through a diode to VDD. This
resistance gives extra noise immunity for detecting the
open state while providing contact wetting current. An
open state is first registered when the SENSE input is
greater than 10.5V. The output of the sensor remains high
until a voltage of < 4.5V is detected at the SENSE input,
representing a valid Ground state, causing the sensor
output to go low. The Sensor will maintain a Ground detect
state until the SENSE input returns to >10.5V. The effect of
the two defined thresholds for Ground and Open
introduces 3 - 6V of hysteresis and provides for a high
degree of noise immunity.
BI
9
C
8
7
6
5
4
3
2
1
First Bit shifted in from SI
Last Bit shifted in from SI
Configuration Register data is loaded serially from the SPI
as described in the Serial Interface section below. The first
bit of the Configuration Register (CR9) enables built-in-self
test when set to a one. For normal sensing operation, CR9
should be zero. The next eight Configuration Register bits
(CR8-1) set the sensing mode for each sensor. If set to a
one, the sensor is GND/Open, and if programmed to a zero
the sensor is Supply/Open. Data is shifted into the
Configuration Register from the serial interface with bit CR9
first.
HOLT INTEGRATED CIRCUITS
4
HI-8428
FUNCTIONAL DESCRIPTION (cont.)
WETTING CURRENT
In Ground/Open mode a current of approximately 1mA is
sourced from the SENSE pin when it is grounded and VDD is
powered at 12.0V. The wetting current serves to provide
current through switches or relay contacts to prevent dry
contacts and improve switch contact reliability.
BUILT-IN TEST
Writing a high in Control Register bit CR9 puts the HI-8428
into the Built-In Test (BIT) mode.
Referring to Figure 1, when in the test mode each of the
internal inputs to the sense comparators are set to either a
high or low. Since the input sense pin is isolated by a
680kΩ resistor, this test mode will not disturb the actual
status of the input pin.
When in BIT mode, setting CRn high for a particular sensor
forces the comparator inputs high. A zero in CRn forces the
comparator input low. To verify correct comparator
behavior, the user must read from the Data Register and
compare with the value written to CR1-8.
NOTE:
Certain flight applications require periodic sensor
testing during flight. To ensure seamless transition
between BIT mode and normal operation mode, the
following steps should be followed:
1) The host should read and record the Configuration
Register value for normal mode operation.
2) The host should read and record the last value of
the Data Register before enabling BIT mode
(CR9 = 1).
3) Following test completion,
but while still in BIT
mode
, the host should set the sensor outputs to
their pre-test values by writing bits CR8 - CR1 with
their corresponding Data Register pre-test values
recorded in step 2) above.
4) Normal operation (CR9 = 0) is restored by writing
the Configuration Register with its pre-test value
stored in step 1).
SUPPLY/OPEN SENSING
When programmed as Supply/Open sensors, CRn is set to a
logic 0. Referring to Figure 1, a switch in series with a diode
is closed to provide a pull down to ground of 30kΩ.
Supply/Open thresholds are set at >12V for the supply state
and <6V for the open state, providing 3 - 6V of hysteresis /
noise rejection.
WETTING CURRENT
For the Supply/Open case the wetting current into the sense
input is simply the current sunk by the effective 30kΩ to
GND. For V
SENSE
= 28V, I
WET
is 1ma. See Figure 2.
HOLT INTEGRATED CIRCUITS
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
