HI-1590
January 2015
MIL-STD-1553/1760
3.3V Monolithic Dual Variable Transceiver
PIN CONFIGURATIONS
DESCRIPTION
The HI-1590 is a low power CMOS dual +3.3V transceiver with
the ability to vary the amplitude of the transmitter outputs. It is
designed to meet the requirements of the MIL-STD-1553 /
1760 specifications, and is pin compatible to the HI-1570. The
HI-1590 adds SPI communication to the onboard DAC to vary
the amplitude of the transmitter outputs.
The transmitter section of each bus takes complementary
CMOS / TTL Manchester II bi-phase data and converts it to
differential voltages suitable for driving the bus isolation
transformer. Separate transmitter inhibit control signals are
provided for each transmitter. The user has the option to either
supply an external voltage to a single analog input pin, or
program an 8-bit DAC through a SPI port to control the
transmitter output amplitude.
The receiver section of each bus converts the 1553 bus bi-
phase differential data to complementary CMOS / TTL data
suitable for inputting to a Manchester decoder. Each receiver
has a separate enable input which can be used to force the
output of the receiver to a logic “0“.
To minimize the package size for this function, the transmitter
outputs are internally connected to the receiver inputs so that
only two pins are required for connection to each coupling
transformer.
44 Pin Plastic 7m
m
x 7mm Chip-scale package
FEATURES
Compliant to MIL-STD-1553A & B, MIL-STD-1760,
ARINC 708A
CMOS technology for low standby power
Single +3.3V power supply
Variable transmitter output amplitude with option to
control with an external voltage or SPI controlled 8-
bit DAC
Smallest footprint available in 7mm x 7mm plastic
chip-scale (QFN) package with integral heatsink
Less than 1.2W maximum power dissipation
Footprint compatible packaging options with HI-1570
or HI-1579
Industrial and extended temperature ranges
Industry standard pin configurations
28 – Pin Ceramic Side-Brazed DIP
(DS1590 Rev. B)
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01/15
HI-1590
BLOCK DIAGRAM
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HI-1590
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SYMBOL
VCONT
BUSA
BUSA
RXENA
GND
VDD
BUSB
BUSB
VDD
CAP
FUNCTION
Analog input
Analog output
Analog output
Digital input
Power supply
Power supply
Analog output
Analog output
Power supply
Analog
DESCRIPTION
Transmit output amplitude control (0-3.3 Vdc, see Figure 8)
MIL-STD-1553 bus driver A, positive signal
MIL-STD-1553 bus driver A, negative signal
Receiver A enable. If low, forces RXA and RXA low
Ground for bus A and bus B
+3.3 volt power for both bus A and bus B
MIL-STD-1553 bus driver B, positive signal
MIL-STD-1553 bus driver B, negative signal
+3.3 volt power for both bus A and bus B
Negative connection for external capacitor C
BUCKET
. See
Table 4 for recommended capacitor type.
Positive connection for external capacitor C
BUCKET
. See
Table 4 for recommended capacitor type.
Positive connection for external capacitor C
RESERVOIR
. See
Table 4 for recommended capacitor type.
Receiver B enable. If low, forces RXB and RXB low
Receiver B output, inverted
Receiver B output, non-inverted
SPI enable. Tri-level inputs. If low, forces DAC value to control the output
amplitude with 0-4.9V range in 19mV step size. If floating, forces VCONT A/B to
control output amplitude. If high, forces DAC value to control the output amplitude
with 0-26V range in 101mV step size
Transmit inhibit, bus B. If high BUSB, BUSB disabled
Transmitter B digital data input, non-inverted
Transmitter B digital data input, inverted
Receiver A output, inverted
Receiver A output, non-inverted
Transmit inhibit, bus A. If high BUSA, BUSA disabled
SPI Clock
SPI Chip Select, Active Low, internal 30KΩ pull-up
SPI serial data output
SPI serial data input, internal 30KΩ pull-up
Transmitter A digital data input, non-inverted
Transmitter A digital data input, inverted
CAP
CRES
RXENB
RXB
RXB
VSEL
TXINHB
TXB
TXB
RXA
RXA
TXINHA
SCK
CSN
SO
SI
TXA
TXA
Analog
Analog
Digital input
Digital output
Digital output
Digital input
Digital input
Digital input
Digital input
Digital output
Digital output
Digital input
Digital input
Digital input
Digital output
Digital input
Digital input
Digital input
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HI-1590
FUNCTIONAL DESCRIPTION
The HI-1590 data bus transceiver contains differential voltage
source drivers and differential receivers. They are intended for
applications using a MIL-STD-1553 A/B data bus. The device
produces a trapezoidal output waveform during transmission.
When pulling VSEL low, the output amplitude (measured
at Point “A
T
“ in Figure 7
)
ranges between 0 – 4.90 Volts
in ~19mV steps as described by the following equation:
Y = 0.019x
(Equation 2)
TRANSMITTER
Data input to the device’s transmitter section is from the
complementary CMOS / TTL inputs TXA/B and TXA/̅B. The
̅ ̅ ̅ ̅
transmitter accepts Manchester II bi-phase data and converts it
to differential voltages on BUSA/B and BUSA/̅B. The
̅ ̅ ̅ ̅ ̅
transceiver outputs are either direct or transformer coupled to
the MIL-STD-1553 data bus. Both coupling methods produce
a nominal voltage on the bus of 7.5 volts peak to peak at
VCONT = 3.3 Vdc or maximum 8-bit DAC value 255. Refer to
Figure 8 and Figure 9 for transmitter output amplitudes at other
values of DAC or VCONT between 0 – 3.3 Vdc.
The transmitter is automatically inhibited and placed in the high
impedance state when both TXA/B and TXA/̅B are either at a
̅ ̅ ̅ ̅
logic “1” or logic “0” simultaneously. A logic “1” applied to the
TXINHA/B input will force the transmitter to the high
impedance state, regardless of the state of TXA/B and TXA/̅B.
̅ ̅ ̅ ̅
Where Y is the output amplitude Vo, and x = DAC values
0
≤
x
≤
255). Figure 10 plots this relationship between
the DAC value input and the output voltage amplitude.
RECEIVER
The receiver accepts bi-phase differential data from the MIL-
STD-1553 bus through the same direct or transformer coupled
interface as the transmitter. The receiver’s differential input
stage drives a filter and threshold comparator that produces
CMOS/TTL data at the RXA/B and RXA/̅B output pins.
̅ ̅ ̅ ̅
Each set of receiver outputs can be independently forced to a
logic "0" by setting RXENA or RXENB low.
DAC (Digital-to-Analog Converter) and VCONT
The 8 bits written into the SPI register are the input to the DAC.
This DAC can control the amplitude of the HI-1590 transmitter
output voltage by pulling VSEL high or low according to the
following table:
MIL-STD-1553 BUS INTERFACE
A direct coupled interface (see Figure 4) uses a 1:2.5 ratio
isolation transformer and two 55
Ω
isolation resistors between
the transformer and the bus.
In a transformer coupled interface (see Figure 4), the
transceiver is also connected to a 1:1.25 isolation transformer
which in turn is connected to a 1:1.4 coupling transformer. The
transformer coupled method also requires two coupling
resistors equal to 75% of the bus characteristic impedance
(Zo) between the coupling transformer and the bus.
VSEL
Control
Source
8-bit DAC
via SPI
V
CONT
analog via
pin 1
8-bit DAC
via SPI
High
Float
Low
Output
Amplitude
Range @ Point
A
T
0 - 26V
0 - 26V
0 – 4.90V
Step Size
(mV)
101mV
Analog
19mV
SERIAL PERIPHERAL INTERFACE (SPI)
BASICS
The HI-1590 uses an SPI synchronous serial interface for host
access to the internal DAC register. Host serial
communication is enabled through the Chip Select CSN pin,
and is accessed via a three-wire interface consisting of Serial
Data Input (SI) from the host, Serial Data output (SO) to the
host and Serial Clock (SCK). All read/write cycles are
completely self-timed.
The SPI (Serial Peripheral Interface) protocol specifies master
and slave operation; the HI-1590 operates as an SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOL-CPHA
combinations define four possible “SPI Modes”. Without
describing details of the SPI modes, the HI-1590 operates in
When pulling VSEL high, the output amplitude
(measured at Point “A
T
“ in Figure 7
)
ranges between 0 –
26 Volts in ~101mV steps as described by the following
equation:
Y = 0.101x
(Equation 1)
Where Y is the output amplitude Vo and x = DAC values
0
≤
x
≤
255. Figure 9 plots this relationship between the
DAC value input and the output voltage amplitude.
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HI-1590
mode 0 where input data for each device (master and slave) is
clocked on the rising edge of SCK, and output data for each
device changes on the falling edge (CPHA = 0, CPOL = 0). Be
sure to set the host SPI logic for mode 0.
As seen in Figure 1, SPI Mode 0 holds SCK in the low state
when idle.
The SPI protocol transfers serial data as 8-bit bytes. Once
CSN chip select is asserted, the next 8 rising edges on SCK
latch input data into the master and slave devices, starting with
each byte’s most-significant bit. The HI-1590 SPI can be
clocked at up to 20MHz.
HI-1590 SPI COMMANDS
For the HI-1590, each SPI operation is both a read and a
simultaneous write. When a host transfers an 8 bit DAC
setting, the current byte in the shift register is shifted out and
read at the SO pin as the new byte is shifted into the register
simultaneously as shown in Figure 1. The newly arrived byte
is transferred from the host to the device on the rising edge of
CSN.
Figure 1: Single-Byte Transfer using SPI Protocol Mode 0
t
CPH
t
CYC
t
CHH
t
CES
t
DS
SI
t
SCKF
t
DH
t
SCKR
t
CEH
Figure 2: SPI Serial Input Timing
t
CPH
t
CYC
t
SCKH
t
SCKL
t
DV
t
CHZ
SO
Figure 3: SPI Serial Output Timing
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