MTV10N100E
Designer’s™ Data Sheet
TMOS E−FET.™
Power Field Effect
Transistor
D
3
PAK for Surface Mount
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N−Channel Enhancement−Mode Silicon
Gate
The D
3
PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor. This
allows it to be used in applications that require surface mount
components with higher power and lower R
DS(on)
capabilities. This
high voltage MOSFET uses an advanced termination scheme to provide
enhanced voltage−blocking capability without degrading performance
over time. In addition, this advanced TMOS E−FET is designed to
withstand high energy in the avalanche and commutation modes. The
new energy efficient design also offers a drain−to−source diode with a
fast recovery time. Designed for high voltage, high speed switching
applications in surface mount PWM motor controls and both ac−dc and
dc−dc power supplies. These devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
•
Robust High Voltage Termination
•
Avalanche Energy Specified
•
Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
•
Diode is Characterized for Use in Bridge Circuits
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
•
Short Heatsink Tab Manufactured
−
Not Sheared
•
Specifically Designed Leadframe for Maximum Power Dissipation
•
Available in 24 mm, 13−inch/500 Unit Tape & Reel, Add
−RL
Suffix
to Part Number
TMOS POWER FET
10 AMPERES, 1000 VOLTS
R
DS(on)
= 1.3
W
D
3
PAK Surface Mount
CASE 433−01
Style 2
N−Channel
D
®
G
S
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 1
1
Publication Order Number:
MTV10N100E/D
MTV10N100E
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage — Continuous
Drain Current — Continuous
Drain Current
— Continuous @ 100°C
Drain Current
— Single Pulse (t
p
≤
10
μs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ T
C
= 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy — Starting T
J
= 25°C
(V
DD
= 100 Vdc, V
GS
= 10 Vdc, Peak I
L
= 10 Apk, L = 10 mH, R
G
= 25
Ω
)
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Thermal Resistance
— Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Symbol
V
DSS
V
DGR
V
GS
I
D
I
D
Value
1000
1000
±20
10
6.2
30
250
2.0
3.57
−55
to 150
500
0.5
62.5
35
260
°C/W
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
W/°C
Watts
°C
mJ
I
DM
P
D
T
J
, T
stg
E
AS
R
θJC
R
θJA
R
θJA
T
L
°C
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2
MTV10N100E
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
μAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 1000 Vdc, V
GS
= 0 Vdc)
(V
DS
= 1000 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±20
Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
μAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (V
GS
= 10 Vdc, I
D
= 5.0 Adc)
Drain−to−Source On−Voltage
(V
GS
= 10 Vdc, I
D
= 10 Adc)
(V
GS
= 10 Vdc, I
D
= 5.0 Adc, T
J
= 125°C)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 5.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(V
DD
= 500 Vdc, I
D
= 10 Adc,
V
GS
= 10 Vdc,
R
G
= 9.1
Ω)
t
d(on)
t
r
t
d(off)
t
f
Q
T
(V
DS
= 400 Vdc, I
D
= 10 Adc,
V
GS
= 10 Vdc)
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 10 Adc, V
GS
= 0 Vdc)
(I
S
= 10 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
V
SD
Vdc
—
—
—
—
—
—
0.885
0.8
885
220
667
8.0
1.1
—
—
—
—
—
μC
nH
—
—
4.5
13
—
nH
—
ns
—
—
—
—
—
—
—
—
29
57
118
70
100
18.4
33
36.7
60
120
240
140
120
—
—
—
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
—
—
—
3500
264
52
5600
530
90
pF
V
GS(th)
Vdc
2.0
—
—
—
—
8.0
3.0
7.0
1.07
11
—
10
4.0
—
1.3
15
15.3
—
mhos
mV/°C
Ohm
Vdc
V
(BR)DSS
Vdc
1000
—
—
—
—
—
1254
—
—
—
—
—
10
100
100
mV/°C
μAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
R
DS(on)
V
DS(on)
g
FS
Reverse Recovery Time
(I
S
= 10 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/μs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width
≤
300
μs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
t
rr
t
a
t
b
Q
RR
L
D
L
S
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3
MTV10N100E
TYPICAL ELECTRICAL CHARACTERISTICS
16
I D , DRAIN CURRENT (AMPS)
20
T
J
= 25°C
V
GS
= 10 V
I D , DRAIN CURRENT (AMPS)
6V
12
5V
8
16
V
DS
≥
10 V
12
8
100°C
4
25°C
T
J
= 55°C
4
4V
0
0
4
8
12
16
20
0
2.8
3.2
3.6
4
4.4
4.8
5.2
5.6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
2.4
2
1.6
1.2
0.8
V
GS
= 10 V
T
J
= 100°C
1.48
T
J
= 25°C
1.4
1.32
1.24
1.16
1.08
1.0
V
GS
= 10 V
15 V
25°C
−55°C
0.4
0
0
4
8
12
16
20
0
4
8
12
16
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2.8
2.4
2
1.6
1.2
0.8
0.4
0
−50
V
GS
= 10 V
I
D
= 5 A
100000
V
GS
= 0 V
10000
I DSS , LEAKAGE (nA)
100°C
T
J
= 125°C
1000
100
10
25°C
−25
0
25
50
75
100
125
150
1
0
100 200
300
400
500
600
700
800
900 10
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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MTV10N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate
of average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to
the on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
inductive; the data in the figure is taken with a resistive load,
which approximates an optimally snubbed inductive load.
Power MOSFETs may be safely operated into an inductive
load; however, snubbing reduces switching losses.
8000
7000
C, CAPACITANCE (pF)
6000
5000
4000
3000
2000
1000
C
rss
C
iss
V
DS
= 0 V
V
GS
= 0 V
10000
T
J
= 25°C
V
GS
= 0 V
C
iss
T
J
= 25°C
C, CAPACITANCE (pF)
1000
C
iss
C
oss
100
C
rss
C
oss
C
rss
10
0
10
5
V
GS
0
V
DS
5
10
15
20
25
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
Figure 7b. High Voltage Capacitance Variation
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