CBTL05023
Multiplexer/demultiplexer switch for Thunderbolt applications
Rev. 2 — 15 August 2012
Product brief
1. General description
The CBTL05023 is a multiplexer/demultiplexer switch chip for DisplayPort v1.2 signals
and the control signals of a 10 Gbit/s channel. The 10 Gbit/s channel does not pass
through this switch. This chip provides BIASOUT output control signal, and the
DC-biasing pull-down resistors to facilitate an external 10 Gbit/s channel.
The AUX MUX is a 2 : 1 switch with CA_DETect pin selecting between AUX and DDC
(Direct Display Control) signals.
The DP MUX is a 2 : 1 switch that selects between DPML (DisplayPort Main Link) and
LSTX/LSRX signals.
This chip also includes three control signal buffers: HPDOUT, CA_DETOUT and
BIASOUT.
CBTL05023 is powered by a 3.3 V supply and it is available in 3 mm
×
3 mm HVQFN24
package with 0.4 mm pitch.
2. Features and benefits
2.1 AUX MUX 2 : 1 switch
This 2 : 1 switch is controlled by CA_DET signal multiplexing of the 1 Mbit/s
differential AUX and DDC (Direct Display Control) signals
When CA_DET is HIGH, DDC path is selected
Differential AUX channel:
Low insertion loss:
−0.5
dB at 5 MHz
Low return loss:
−19
dB at 5 MHz
Low ON-state resistance: 7.5
Ω
Bandwidth: 5 GHz
Low off-state isolation:
−75
dB at 5 MHz
Low crosstalk:
−40
dB at 5 MHz
Common-mode input voltage V
IC
: 0 V to 3.3 V
Differential input voltage V
ID
: 1.4 V (maximum)
DDC channel has DDC_CLK and DDC_DAT I
2
C signals
100 kHz 3.3 V voltage swing
Both AUXIO+ and AUXIO− outputs have 900
Ω
(±20 %) pull-down resistor that is
enabled by the status of the BIASOUT output pin
These pull-down resistors provide DC bias for the 10 Gbit/s channel
NXP Semiconductors
CBTL05023
Multiplexer/de-multiplexer switch for Thunderbolt applications
2.2 DP MUX 2 : 1 switch
The DP MUX is a 2:1 switch that is controlled by DP_PD pin multiplexing of a differential
DPML signal and LSTX/LSRX signals
The DPML (DisplayPort Main Link) runs up to HBR2 data rate of 5.4 Gbit/s
The low speed DC coupled signals LSTX and LSRX are 3.3 V single-ended signals
that operated at 1 Mbit/s
5.4 Gbit/s DPML channel:
Low insertion loss for DP-DPMLO path:
−2.0
dB at 2.5 GHz
Low insertion loss for LS-DPMLO path:
−2.0
dB at 2.5 GHz
Low return loss for DP-DPMLO path:
−15
dB at 2.5 GHz
Low return loss for LS-DPMLO path:
−14
dB at 2.5 GHz
Low ON-state resistance for DP-DPMLO path: 9
Ω
Low ON-state resistance for LS-DPMLO path: 13
Ω
High bandwidth: 7 GHz
Low off-state isolation:
−20
dB at 2.5 GHz
Low crosstalk:
−25
dB at 2.5 GHz
Common-mode input voltage V
IC
: 0 V to 3.3 V
Differential input voltage V
ID
: 1.4 V (maximum)
2.3 General
The input of the HPDOUT (Hug Plug Detect output) buffer is 5 V tolerant
HPDOUT, CA_DETOUT and BIASOUT buffers
CA_DET input leakage current < 0.1
μA
to prevent driving the 1 MΩ pull-down to a
HIGH level
BIASOUT buffer is able to provide enough current to drive the bias circuit for the
PIN diode path
BIASOUT buffer can drive up to six sets of bias circuits for the 10 Gbit/s paths
When AUXIO_EN is LOW or (BIASIN = 0 and DP_PD = 1), this chip is in Sleep mode
AUXIO+ and AUXIO− of AUX MUX are disabled
CA_DETOUT and HPDOUT buffers are on
When the chip is in Sleep mode, CBTL05023 will consume < 3.5 mW
Patent-pending high-bandwidth analog pass-gate technology
Very low intra-pair differential skew (5 ps typical)
All channels have back current protection
All channels support rail-to-rail input voltage
CMOS input buffer with hysteresis
Single 3.3 V
±
10 % power supply
HVQFN24 3 mm
×
3 mm package, 0.4 mm pitch, with exposed center pad for thermal
relief and electrical ground
ESD: 2500 V HBM, 1250 V CDM
Operating temperature range: 0
°C
to 85
°C
CBTL05023
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product brief
Rev. 2 — 15 August 2012
2 of 4
NXP Semiconductors
CBTL05023
Multiplexer/de-multiplexer switch for Thunderbolt applications
3. Ordering information
Table 1.
Ordering information
Package
Name
CBTL05023BS
HVQFN24
Description
plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 3
×
3
×
0.85 mm
[1]
Version
SOT905-1
Type number
[1]
Maximum package height is 1 mm.
4. Pinning information
4.1 Pinning
BIASOUT
20 DPMLO−
19 DPMLO+
DP+ 11
23 AUXIO−
22 AUXIO+
CA_DET
HPDOUT
002aag230
terminal 1
index area
21 GND
BIASIN 1
AUXIO_EN 2
V
DD
3
DDC_DAT 4
DDC_CLK 5
6
AUX− 7
AUX+ 8
GND 9
DP− 10
CBTL05023BS
DP_PD
Transparent top view
Center pad is connected to printed-circuit board ground plane for electrical grounding and
thermal relief.
Fig 1.
Pin configuration for HVQFN24
CBTL05023
All information provided in this document is subject to legal disclaimers.
12
18
17 HPD
16 CA_DETOUT
15 V
DD
14 LSTX
13 LSRX
24
© NXP B.V. 2012. All rights reserved.
Product brief
Rev. 2 — 15 August 2012
3 of 4
NXP Semiconductors
CBTL05023
Multiplexer/de-multiplexer switch for Thunderbolt applications
5. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 3 x 3 x 0.85 mm
D
B
A
SOT905-1
terminal 1
index area
E
A
A
1
c
detail X
e
1
e
6
7
C
b
11
12
b
1
v
w
M
M
C A B
C
y
1
C
y
L
13
5
e
E
h
b
1
e
2
1
17
LC
terminal 1
index area
24
23
19
18
D
h
LC
0
L
1
X
1.5
scale
3 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
(1)
max
1
A
1
0.05
0.00
b
0.25
0.15
b
1
0.45
0.35
c
0.2
D
(1)
3.1
2.9
D
h
2.05
1.75
E
(1)
3.1
2.9
E
h
2.05
1.75
e
0.4
e
1
1.8
e
2
1.8
L
0.35
0.15
L
1
0.1
0.0
LC
0.3
0.2
v
0.1
w
0.05
y
0.05
y
1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included
OUTLINE
VERSION
SOT905-1
REFERENCES
IEC
---
JEDEC
---
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
06-03-13
06-03-31
Fig 2.
Package outline SOT905-1 (HVQFN24)
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 August 2012
Document identifier: CBTL05023
CBTL05023
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product brief
Rev. 2 — 15 August 2012
4 of 4
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