CBTL04082A; CBTL04082B
3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer
switch for PCI Express Gen2
Rev. 1 — 28 February 2011
Product data sheet
1. General description
CBTL04082A/B is an 8-to-4 bidirectional differential channel multiplexer/demultiplexer
switch for PCI Express Generation 2 (Gen2) applications. The CBTL04082A/B can switch
four differential signals to one of two locations. Using a unique design technique, NXP has
minimized the impedance of the switch such that the attenuation observed through the
switch is negligible, and also minimized the channel-to-channel skew as well as
channel-to-channel crosstalk, as required by the high-speed serial interface.
CBTL04082A/B allows expansion of existing high speed ports for extremely low power.
The devices’ pinouts are optimized to match different application layouts. CBTL04082A
has input and output pins on the opposite of the package, and is suitable for edge
connector(s) with different signal sources on the motherboard. CBTL04082B has outputs
on both sides of the package, and the device can be placed between two connectors to
multiplex differential signals from a controller. Please refer to
Section 8
for layout
examples.
2. Features and benefits
4 bidirectional differential channel, 2 : 1 multiplexer/demultiplexer
High-speed signal switching for PCIe Gen2 5 Gbit/s
High bandwidth: 6 GHz at
−3
dB
Insertion loss:
−0.5
dB at 100 MHz
−1.2
dB at 2.5 GHz
Low intra-pair skew: 5 ps typical
Low inter-pair skew: 35 ps maximum
Low crosstalk:
−30
dB at 2.5 GHz
Low off-state isolation:
−25
dB at 2.5 GHz
Low return loss:
−20
dB at 2.5 GHz
V
DD
operating range: 3.3 V
±
10 %
Dual shutdown pins for channel 0/1 and 2/3 independently to minimize power
consumption
Standby current less than 1
μA
ESD tolerance:
8 kV HBM
1 kV CDM
HVQFN42 package
NXP Semiconductors
CBTL04082A; CBTL04082B
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
3. Applications
Routing of high-speed differential signals with low signal attenuation
PCIe Gen2
DisplayPort 1.2
USB 3.0
SATA 6 Gbit/s
4. Ordering information
Table 1.
Ordering information
Package
Name
CBTL04082ABS
CBTL04082BBS
HVQFN42
HVQFN42
Description
plastic thermal enhanced very thin quad flat package; no leads;
42 terminals; body 3.5
×
9
×
0.85 mm
[1]
plastic thermal enhanced very thin quad flat package; no leads;
42 terminals; body 3.5
×
9
×
0.85 mm
[1]
Version
SOT1144-1
SOT1144-1
Type number
[1]
Total height after printed-circuit board mounting = 1.0 mm (maximum).
5. Functional diagram
A0_P
A0_N
A1_P
A1_N
B0_P
B0_N
B1_P
B1_N
C0_P
C0_N
XSD01
C1_P
C1_N
A2_P
A2_N
A3_P
A3_N
B2_P
B2_N
B3_P
B3_N
C2_P
C2_N
XSD23
C3_P
C3_N
SEL
002aaf752
Fig 1.
Functional diagram of CBTL04082A; CBTL04082B
CBTL04082A_CBTL04082B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 28 February 2011
2 of 18
NXP Semiconductors
CBTL04082A; CBTL04082B
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
6. Pinning information
6.1 Pinning
CBTL04082ABS
41 XSD01
39 GND
42 V
DD
40 V
DD
CBTL04082BBS
40 XSD01
42 GND
41 V
DD
39 n.c.
38 GND
37 B0_P
36 B0_N
35 GND
34 V
DD
33 B1_P
32 B1_N
31 V
DD
30 SEL
29 GND
28 B2_P
27 B2_N
26 V
DD
25 GND
GND
(exposed
thermal pad)
GND 18
V
DD
19
XSD23 20
V
DD
21
24 B3_P
23 B3_N
22 GND
002aaf710
© NXP B.V. 2011. All rights reserved.
GND
A0_P
A0_N
GND
V
DD
A1_P
A1_N
n.c.
SEL
1
2
3
4
5
6
7
8
9
38 B0_P
37 B0_N
36 B1_P
35 B1_N
34 C0_P
33 C0_N
32 C1_P
31 C1_N
30 V
DD
29 B2_P
28 B2_N
27 B3_P
26 B3_N
25 C2_P
GND
(exposed
thermal pad)
n.c. 18
XSD23 19
V
DD
20
GND 21
24 C2_N
23 C3_P
22 C3_N
A0_P
A0_N
C0_P
C0_N
A1_P
A1_N
C1_P
C1_N
V
DD
1
2
3
4
5
6
7
8
9
GND 10
A2_P 11
A2_N 12
V
DD
13
GND 14
A3_P 15
A3_N 16
GND 17
A2_P 10
A2_N 11
C2_P 12
C2_N 13
A3_P 14
A3_N 15
C3_P 16
C3_N 17
002aaf754
Transparent top view
Transparent top view
a. CBTL04082A
Fig 2.
Pin configuration for HVQFN42
b. CBTL04082B
6.2 Pin description
Table 2.
Symbol
A0_P
A0_N
A1_P
A1_N
A2_P
A2_N
A3_P
A3_N
Pin description
Pin
CBTL04082A
2
3
6
7
11
12
15
16
CBTL04082B
1
2
5
6
10
11
14
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
channel 3, port A differential signal input/output
channel 2, port A differential signal input/output
channel 1, port A differential signal input/output
channel 0, port A differential signal input/output
Type
Description
CBTL04082A_CBTL04082B
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 — 28 February 2011
3 of 18
NXP Semiconductors
CBTL04082A; CBTL04082B
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
Table 2.
Symbol
B0_P
B0_N
B1_P
B1_N
B2_P
B2_N
B3_P
B3_N
C0_P
C0_N
C1_P
C1_N
C2_P
C2_N
C3_P
C3_N
SEL
Pin description
…continued
Pin
CBTL04082A
38
37
36
35
29
28
27
26
34
33
32
31
25
24
23
22
9
CBTL04082B
37
36
33
32
28
27
24
23
3
4
7
8
12
13
16
17
30
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CMOS
single-ended
input
CMOS
single-ended
input
CMOS
single-ended
input
power
operation mode select
SEL = LOW: A
↔
B
SEL = HIGH: A
↔
C
Shutdown pin; should be driven LOW or connected to GND for
normal operation. When HIGH, channel 0 and channel 1 are
switched off (non-conducting high-impedance state), and
supply current consumption is minimized.
Shutdown pin; should be driven LOW or connected to GND for
normal operation. When HIGH, channel 2 and channel 3 are
switched off (non-conducting high-impedance state), and
supply current consumption is minimized.
positive supply voltage, 3.3 V (±10 %)
supply ground
channel 3, port C differential signal input/output
channel 2, port C differential signal input/output
channel 1, port C differential signal input/output
channel 0, port C differential signal input/output
channel 3, port B differential signal input/output
channel 2, port B differential signal input/output
channel 1, port B differential signal input/output
channel 0, port B differential signal input/output
Type
Description
XSD01
41
40
XSD23
19
20
V
DD
GND
[1]
5, 13, 20, 30,
40, 42
1, 4, 10, 14,
17, 21, 39,
center pad
8, 18
9, 19, 21, 26,
31, 34, 41
18, 22, 25, 29, power
35, 38, 42,
center pad
39
-
n.c.
not connected; these pins can be connected to any signal
externally
[1]
HVQFN42 package die supply ground is connected to both GND pins and exposed center pad. GND pins and the exposed center pad
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the
exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through
the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
CBTL04082A_CBTL04082B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 28 February 2011
4 of 18
NXP Semiconductors
CBTL04082A; CBTL04082B
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
7. Functional description
Refer to
Figure 1 “Functional diagram of CBTL04082A; CBTL04082B”.
7.1 Function selection
Table 3.
Function selection
X = Don’t care.
XSD01
HIGH
LOW
LOW
-
-
-
XSD23
-
-
-
HIGH
LOW
LOW
SEL
X
LOW
HIGH
X
LOW
HIGH
Function
An, Bn and Cn pins are high-Z, n = 0, 1
An to Bn or vice versa, n = 0, 1
An to Cn or vice versa, n = 0, 1
An, Bn and Cn pins are high-Z, n = 2, 3
An to Bn or vice versa, n = 2, 3
An to Cn or vice versa, n = 2, 3
7.2 Shutdown function
The CBTL04082A/B provides a shutdown function to minimize power consumption when
the application is not active, but power to the CBTL04082A/B is provided. Pin XSD01 and
XSD23 (active HIGH) places channel 0/1 and 2/3 (respectively) in high-impedance state
(non-conducting) while reducing current consumption to near-zero.
Table 4.
XSD01
HIGH
LOW
-
-
Shutdown function
XSD23
-
-
HIGH
LOW
Channel 0
high-Z
active
-
-
Channel 1
high-Z
active
-
-
Channel 2
-
-
high-Z
active
Channel 3
-
-
high-Z
active
CBTL04082A_CBTL04082B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 28 February 2011
5 of 18
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
