CAT5261
Dual Digital
Potentiometer (POT)
with 256 Taps
and SPI Interface
Description
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The CAT5261 is two digital POTs integrated with control logic and
8 bytes of NVRAM memory. Each digital POT consists of a series of
resistive elements connected between two externally accessible end
points. The tap points between each resistive element are connected to
the wiper outputs with CMOS switches. A separate 8-bit control
register (WCR) independently controls the wiper tap switches for each
digital POT. Associated with each wiper control register are four 8-bit
non-volatile memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or any of the
non-volatile data registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the potentiometers
is automatically loaded into its respective wiper control register.
The CAT5261 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications. It is available in the
−40C
to 85C industrial operating temperature range and offered in a
24-lead SOIC and TSSOP package.
Features
TSSOP−24
Y SUFFIX
CASE 948AR
SOIC−24
W SUFFIX
CASE 751BK
PIN CONNECTIONS
SO
A0
NC
NC
NC
NC
V
CC
R
L0
R
H0
R
W0
CS
WP
SOIC−24 (W)
TSSOP−24 (Y)
(Top View)
CAT5261
1
HOLD
SCK
NC
NC
NC
NC
GND
R
W1
R
H1
R
L1
A1
SI
Two Linear-taper Digital Potentiometers
256 Resistor Taps per Potentiometer
End to End Resistance 50 kW or 100 kW
Potentiometer Control and Memory Access via SPI Interface
Low Wiper Resistance, Typically 100
W
Nonvolatile Memory Storage for up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1
mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
24-lead SOIC and 24-lead TSSOP
Industrial Temperature Range
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013
−
Rev. 8
1
Publication Order Number:
CAT5261/D
CAT5261
MARKING DIAGRAMS
(SOIC−24)
(TSSOP−24)
L3B
CAT5261WT
−RRYMXXXX
RLB
CAT5261YI
3YMXXX
L = Assembly Location
3 = Lead Finish
−
Matte-Tin
B = Product Revision (Fixed as “B”)
CAT = Fixed as “CAT”
5261W = Device Code
T = Temperature Range (I = Industrial)
−
= Dash
RR = Resistance
25 = 2.5 KW
10 = 10 KW
50 = 50 KW
00 = 100 KW
Y = Production Year (Last Digit)
M = Production Month (1-9, O, N, D)
XXXX = Last Four Digits of Assembly Lot Number
R = Resistance
1 = 2.5 KW
2 = 10 KW
4 = 50 KW
5 = 100 KW
L = Assembly Location
B = Product Revision (Fixed as “B”)
CAT5261Y = Device Code
I = Temperature Range (I = Industrial)
3 = Lead Finish
−
Matte-Tin
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
R
H0
CS
SCK
SI
SO
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R
H1
R
W0
R
W1
WP
A0
A1
HOLD
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R
L0
R
L1
Figure 1. Functional Diagram
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CAT5261
PIN DESCRIPTIONS
Table 1. PIN DESCRIPTIONS
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
SO
A0
NC
NC
NC
NC
V
CC
R
L0
R
H0
R
W0
CS
WP
SI
A1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCK
HOLD
Function
Serial Data Output
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
Wiper Terminal for Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal for
Potentiometer 1
High Reference Terminal for
Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Hold
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5261. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT5261. During a read cycle, data is shifted
out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT5261. Opcodes, byte addresses or data present on the SI
pin are latched on the rising edge of the SCK. Data on the SO
pin is updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be addressed on
a single bus. A match in the slave address must be made with
the address input in order to initiate communication with the
CAT5261.
R
H
, R
L
: Resistor End Points
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
: Wiper
The RW pins are equivalent to the wiper terminal of a
mechanical potentiometer.
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT5261 and
CS high disables the CAT5261. CS high takes the SO output
pin to high impedance and forces the devices into a Standby
mode (unless an internal write operation is underway). The
CAT5261 draws ZERO current in the Standby mode. A high
to low transition on CS is required prior to any sequence
being initiated. A low to high transition on CS after a valid
write sequence is what initiates an internal write cycle.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will allow
normal read/write operations when held high. When WP is
tied low, all non-volatile write operations to the Data
registers are inhibited (change of wiper control register is
allowed). WP going low while CS is still low will interrupt
a write to the registers. If the internal write cycle has already
been initiated, WP going low will have no effect on any write
operation.
HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT5261 while in the middle of a serial sequence without
having to retransmit entire sequence at a later time. To pause,
HOLD must be brought low while SCK is low. The SO pin
is in a high impedance state during the time the part is
paused, and transitions on the SI pins will be ignored. To
resume communication, HOLD is brought high, while SCK
is low. (HOLD should be held high any time this function is
not being used.) HOLD may be tied high directly to V
CC
or
tied to V
CC
through a resistor.
WP: Write Protect Input
The WP pin when tied low prevents non-volatile writes to
the device (change of wiper control register is allowed) and
when tied high or left floating normal read/write operations
are allowed.
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CAT5261
SERIAL BUS PROTOCOL
The CAT5261 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface (SPI)
helps the CAT5261 to interface directly with many of
today’s popular microcontrollers. The CAT5261 contains an
8-bit instruction register. The instruction set and the
operation codes are detailed in the Instruction Set Table 13
on page 9.
DEVICE OPERATION
The CAT5261 is two resistor arrays integrated with an SPI
serial interface logic, two 8-bit wiper control registers and
eight 8-bit, non-volatile memory data registers. Each
resistor array contains 255 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
). R
H
and R
L
are symmetrical and
may be interchanged. The tap positions between and at the
ends of the series resistors are connected to the output wiper
terminals (R
W
) by a After the device is selected with CS
going low the first byte will be received. The part is accessed
via the SI pin, with data being clocked in on the rising edge
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25C)
Lead Soldering Temperature (10 s)
Wiper Current
Ratings
−55
to +125
−65
to +150
−2.0
to +V
CC
+ 2.0
−0.2
to +7.0
1.0
300
6
Units
C
C
V
V
W
C
mA
of SCK. The first byte contains one of the six op-codes that
define the operation to be performed.
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time and
is determined by the value of the wiper control register. Data
can be read or written to the wiper control registers or the
non-volatile memory data registers via the SPI bus.
Additional instructions allows data to be transferred
between the wiper control registers and each respective
potentiometer’s non-volatile data registers. Also, the device
can be instructed to operate in an “increment/decrement”
mode.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameters
V
CC
Industrial Temperature
Ratings
+2.5 to +6.0
−40
to +85
Units
V
C
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CAT5261
Table 4. POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
R
POT
R
POT
Parameter
Potentiometer Resistance (−00)
Potentiometer Resistance (−50)
Potentiometer Resistance Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
VN
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity (Note 4)
Relative Linearity (Note 5)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
Rw(n)(actual)−R(n)(expected)
(Note 7)
Rw(n+1)−[Rw(n)+LSB]
(Note 7)
(Note 3)
(Note 3)
(Note 3)
R
POT
= 50 kW (Note 3)
10/10/25
0.4
300
20
(Note 3)
0.4
1
0.2
I
W
=
3
mA @ V
CC
= 3 V
I
W
=
3
mA @ V
CC
= 5 V
0
200
100
25C, each pot
Test Conditions
Min
Typ
100
50
20
1
50
3
300
150
V
CC
Max
Units
kW
kW
%
%
mW
mA
W
W
V
nVHz
%
LSB
(Note 6)
LSB
(Note 6)
ppm/C
ppm/C
pF
MHz
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+1 V.
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
6. LSB = R
TOT
/ 255 or (R
H
−
R
L
) / 255, single pot
7. n = 0, 1, 2, ..., 255
Table 5. D.C. OPERATING CHARACTERISTICS
(V
CC
= +2.5 V to +6.0 V, unless otherwise specified.)
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OH1
Parameter
Power Supply Current
Power Supply Current
Non-volatile WRITE
Standby Current (V
CC
= 5 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3 V)
Output High Voltage
I
OL
= 3 mA
I
OH
=
−1.6
mA
V
CC
– 0.8
Test Conditions
f
SCL
= 400 kHz, SDA = Open
V
CC
= 6 V, Inputs = GNDs
f
SCK
= 400 kHz, SDA Open
V
CC
= 6 V, Input = GND
V
IN
= GND or V
CC
, SDA = Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
−1
V
CC
x 0.7
1
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
mA
mA
mA
V
V
V
V
Min
Max
1
5
Units
mA
mA
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