BUK9Y3R0-40E
12 February 2013
LF
PA
K
N-channel 40 V 3.0 mΩ logic level MOSFET in LFPAK56
Product data sheet
1. General description
Logic level N-channel MOSFET in LFPAK56 (Power SO8) package using TrenchMOS
technology. This product has been designed and qualified to AEC Q101 standard for use
in high performance automotive applications.
2. Features and benefits
•
•
•
•
Q101 compliant
Repetitive avalanche rated
Suitable for thermally demanding environments due to 175 °C rating
True logic level gate with V
GS(th)
rating of greater than 0.5 V at 175 °C
3. Applications
•
•
•
•
•
12 V Automotive systems
Motors, lighting and solenoid control
Start-Stop micro-hybrid applications
Transmission control
Ultra high performance power switching
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
V
GS
= 5 V; T
mb
= 25 °C;
Fig. 1
T
mb
= 25 °C;
Fig. 2
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
[1]
Min
-
-
-
Typ
-
-
-
Max
40
100
194
Unit
V
A
W
Static characteristics
drain-source on-state
resistance
gate-drain charge
-
2.47
3
mΩ
Dynamic characteristics
Q
GD
V
GS
= 5 V; I
D
= 25 A; V
DS
= 32 V;
Fig. 13; Fig. 14
[1]
Continuous current is limited by package.
-
10.7
-
nC
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NXP Semiconductors
BUK9Y3R0-40E
N-channel 40 V 3.0 mΩ logic level MOSFET in LFPAK56
5. Pinning information
Table 2.
Pin
1
2
3
4
mb
Pinning information
Symbol Description
S
S
S
G
D
source
source
source
gate
mounting base; connected to
drain
1 2 3 4
G
mbb076
Simplified outline
mb
Graphic symbol
D
S
LFPAK; Power-
SO8 (SOT669)
6. Ordering information
Table 3.
Ordering information
Package
Name
BUK9Y3R0-40E
LFPAK;
Power-SO8
Description
plastic single-ended surface-mounted package; 4 leads
Version
SOT669
Type number
7. Marking
Table 4.
Marking codes
Marking code
93E040
Type number
BUK9Y3R0-40E
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
R
GS
= 20 kΩ
T
j
≤ 175 °C; DC
T
j
≤ 175 °C; Pulsed
I
D
drain current
T
mb
= 25 °C; V
GS
= 5 V;
Fig. 1
T
mb
= 100 °C; V
GS
= 5 V;
Fig. 1
I
DM
P
tot
BUK9Y3R0-40E
Min
-
-
-10
[1][2]
[3]
[3]
Max
40
40
10
15
100
100
718
194
Unit
V
V
V
V
A
A
A
W
-15
-
-
-
-
peak drain current
total power dissipation
T
mb
= 25 °C; pulsed; t
p
≤ 10 µs;
Fig. 4
T
mb
= 25 °C;
Fig. 2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
12 February 2013
2 / 13
NXP Semiconductors
BUK9Y3R0-40E
N-channel 40 V 3.0 mΩ logic level MOSFET in LFPAK56
Symbol
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Parameter
storage temperature
junction temperature
Conditions
Min
-55
-55
Max
175
175
Unit
°C
°C
Source-drain diode
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
I
D
= 100 A; V
sup
≤ 40 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped;
Fig. 3
[1]
[2]
[3]
[4]
[5]
200
[3]
-
-
100
718
A
A
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
[4][5]
-
193.8
mJ
Accumulated pulse duration up to 50 hours delivers zero defect ppm
Significantly longer life times are achieved by lowering T
j
and or V
GS
Continuous current is limited by package.
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Refer to application note AN10273 for further information.
003aaj065
I
D
(A)
120
P
der
(%)
80
03aa16
160
120
(1)
80
40
40
0
0
30
60
90
120
150
T
j
(°C)
180
0
0
50
100
150
T
mb
(°C)
200
(1) Capped at 100A due to package
Fig. 1.
Continuous drain current as a function of
mounting base temperature
Fig. 2.
Normalized total power dissipation as a
function of mounting base temperature
BUK9Y3R0-40E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
12 February 2013
3 / 13
NXP Semiconductors
BUK9Y3R0-40E
N-channel 40 V 3.0 mΩ logic level MOSFET in LFPAK56
I
AL
(A)
10
3
003aaj066
10
2
(1)
10
(2)
(3)
1
10
-1
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig. 3.
Avalanche rating; avalanche current as a function of avalanche time
I
D
(A)
10
3
Limit R
DSon
= V
DS
/ I
D
10
2
003aaj067
t
p
= 10 us
100 us
10
DC
1 ms
10 ms
1
100 ms
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig. 4.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
Conditions
Fig. 5
Min
-
Typ
-
Max
0.77
Unit
K/W
BUK9Y3R0-40E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
12 February 2013
4 / 13
NXP Semiconductors
BUK9Y3R0-40E
N-channel 40 V 3.0 mΩ logic level MOSFET in LFPAK56
Z
th(j-mb)
(K/W)
1
δ = 0.5
0.2
003aaj068
10
-1
0.1
0.05
0.02
single shot
P
δ=
t
p
T
10
-2
t
p
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
T
t
p
(s)
1
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
Fig. 9; Fig. 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
Fig. 9
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
Fig. 9
I
DSS
drain leakage current
V
DS
= 40 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 40 V; V
GS
= 0 V; T
j
= 175 °C
I
GSS
gate leakage current
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
V
GS
= 5 V; I
D
= 25 A; T
j
= 175 °C;
Fig. 12; Fig. 11
Dynamic characteristics
Q
G(tot)
Q
GS
BUK9Y3R0-40E
Min
40
36
1.4
-
0.5
-
-
-
-
-
-
-
Typ
-
-
1.7
-
-
0.13
-
2
2
2.47
1.98
-
Max
-
-
2.1
2.45
-
10
500
100
100
3
2.5
6
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Static characteristics
V
GS(th)
total gate charge
gate-source charge
I
D
= 25 A; V
DS
= 32 V; V
GS
= 5 V;
Fig. 13; Fig. 14
All information provided in this document is subject to legal disclaimers.
-
-
35.5
11.7
-
-
nC
nC
© NXP B.V. 2013. All rights reserved
Product data sheet
12 February 2013
5 / 13
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