BUK9MJJ-55PTT
Dual TrenchPLUS logic level FET
Rev. 01 — 14 May 2009
Product data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode field-effect power transistor in SO20. Device is
manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring
very low on-state resistance, integrated current sensing transistors and over temperature
protection diodes.
1.2 Features and benefits
Integrated current sensors
Integrated temperature sensors
1.3 Applications
Lamp switching
Motor drive systems
Power distribution
Solenoid drivers
1.4 Quick reference data
Table 1.
Quick reference
Conditions
V
GS
= 5 V; I
D
= 10 A;
T
j
= 25 °C; see
Figure 16;
see
Figure 17
T
j
= 25 °C; V
GS
= 5 V; see
Figure 18
T
j
= 25 °C; V
GS
= 0 V;
I
D
= 250 µA
Min
-
Typ
13
Max
15
Unit
mΩ
Symbol Parameter
R
DSon
drain-source
on-state resistance
ratio of drain current
to sense current
Static characteristics, FET1 and FET2
I
D
/I
sense
5850
55
6500
-
7150
-
A/A
V
V
(BR)DSS
drain-source
breakdown voltage
NXP Semiconductors
BUK9MJJ-55PTT
Dual TrenchPLUS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pinning information
Symbol
G1
IS1
D1
A1
C1
G2
IS2
D2
A2
C2
D2
KS2
S2
S2
D2
D1
KS1
S1
S1
D1
Description
gate 1
current sense 1
drain 1
anode 1
cathode 1
gate 2
current sense 2
drain 2
anode 2
cathode 2
drain 2
Kelvin source 2
source 2
source 2
drain 2
drain 1
Kelvin source 1
source 1
source 1
drain 1
1
10
20
11
D1
A1
D2
A2
Simplified outline
Graphic symbol
FET1
FET2
SOT163-1
(SO20)
G1
IS1 S1 KS1 C1 G2
IS2 S2 KS2 C2
003aaa745
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9MJJ-55PTT
SO20
Description
plastic small outline package; 20 leads; body width 7.5 mm
Version
SOT163-1
Type number
BUK9MJJ-55PTT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 14 May 2009
2 of 15
NXP Semiconductors
BUK9MJJ-55PTT
Dual TrenchPLUS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
T
sp
= 25 °C; V
GS
= 5 V; see
Figure 3;
see
Figure 2; [1][2]
T
sp
= 100 °C; V
GS
= 5 V; see
Figure 2;
T
sp
= 25 °C; t
p
≤
10 µs; pulsed; see
Figure 3
T
sp
= 25 °C; see
Figure 1
[1][2]
Conditions
25 °C < T
j
< 150 °C
R
GS
= 20 kΩ; 25 °C < T
j
< 150 °C
Min
-
-
-15
-
-
-
-
-55
-55
-
Max
55
55
15
12.9
8.1
230
4.5
150
150
100
Unit
V
V
V
A
A
A
W
°C
°C
V
In accordance with the Absolute Maximum Rating System (IEC 60134).
Limiting Values, FET1 and FET2
V
isol(FET-TSD)
FET to temperature
sense diode isolation
voltage
Source-drain diode, FET1 and FET2
I
S
I
SM
E
DS(AL)S
source current
peak source current
T
sp
= 25 °C;
t
p
≤
10 µs; pulsed; T
sp
= 25 °C
[3][4]
[5]
[2][1]
-
-
-
6.5
230
527
A
A
mJ
Avalanche ruggedness, FET1 and FET2
non-repetitive
I
D
= 12.9 A; V
sup
≤
55 V; V
GS
= 5 V; T
j(init)
= 25 °C;
drain-source avalanche unclamped; see
Figure 4;
energy
electrostatic discharge
voltage
HBM; C = 100 pF; R = 1.5 kΩ; pins 3, 16 and 20 to
pins 1, 2, 17, 18 and 19 shorted
HBM; C = 100 pF; R = 1.5 kΩ; pins 8, 11 and 15 to
pins 6, 7, 12,13 and 14 shorted
HBM; C = 100 pF; R = 1.5 kΩ; all pins
[1]
[2]
[3]
[4]
[5]
Single device conducting.
Current is limited by chip power dissipation rating.
Single-pulse avalanche rating limited by maximum junction temperature of 150 °C.
Repetitive rating defined in avalanche rating figure.
Refer to application note AN10273 for further information.
Electrostatic discharge, FET1 and FET2
V
ESD
-
-
-
4
4
0.15
kV
kV
kV
BUK9MJJ-55PTT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 14 May 2009
3 of 15
NXP Semiconductors
BUK9MJJ-55PTT
Dual TrenchPLUS logic level FET
120
P
der
(%)
80
003aab388
15
I
D
(A)
003aab887
10
40
5
0
0
50
100
150
T
sp
200
(°C)
0
0
50
100
150
T
sp
(°C)
200
Fig 2.
Fig 1.
Normalized total power dissipation as a
function of solder point temperature, FET1 and
FET2
Continuous drain current as a function of
solder point temperature, FET1 and FET2
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
003aab894
t
p
= 10
μ
s
100
μ
s
10
1 ms
10 ms
1
DC
10
-1
100 ms
10
-2
10
-1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and
FET2
BUK9MJJ-55PTT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 14 May 2009
4 of 15
NXP Semiconductors
BUK9MJJ-55PTT
Dual TrenchPLUS logic level FET
10
2
I
AL
(A)
003aab924
(1)
10
(2)
1
(3)
10
-1
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig 4.
Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and
FET2
5. Thermal characteristics
Table 5.
Symbol
R
th(j-sp)
R
th(j-a)
Thermal characteristics
Parameter
Conditions
Min
-
-
-
Typ
-
-
73
Max
28
28
-
Unit
K/W
K/W
K/W
thermal resistance from FET1
junction to solder point FET2
thermal resistance from mounted on a printed-circuit board; Both
junction to ambient
channels conducting; zero heat sink area;
see
Figure 5;
see
Figure 6
mounted on a printed-circuit board; Both
channels conducting; 200 mm
2
copper
heat sink area; see
Figure 5;
see
Figure 7
mounted on a printed-circuit board; Both
channels conducting; 400 mm
2
copper
heat sink area; see
Figure 5;
see
Figure 8
mounted on a printed-circuit board; One
channel conducting; zero heat sink area;
see
Figure 5;
see
Figure 6
mounted on a printed-circuit board; One
channel conducting; 200 mm
2
copper heat
sink area; see
Figure 5;
see
Figure 7
mounted on a printed-circuit board; One
channel conducting; 400 mm
2
copper heat
sink area; see
Figure 5;
see
Figure 8
-
60
-
K/W
-
51
-
K/W
-
105
-
K/W
-
90
-
K/W
-
78
-
K/W
BUK9MJJ-55PTT_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 14 May 2009
5 of 15
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