BUK9MGP-55PTS
Dual TrenchPLUS logic level FET
Rev. 01 — 14 May 2009
Product data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode field-effect power transistor in SO20. Device is
manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring
very low on-state resistance, integrated current sensing transistors and over temperature
protection diodes.
1.2 Features and benefits
Integrated current sensors
Integrated temperature sensors
1.3 Applications
Lamp switching
Motor drive systems
Power distribution
Solenoid drivers
1.4 Quick reference data
Table 1.
Quick reference
Conditions
V
GS
= 5 V; I
D
= 10 A;
T
j
= 25 °C; see
Figure 23;
see
Figure 25
T
j
= 25 °C; V
GS
= 5 V; see
Figure 27
V
GS
= 0 V; I
D
= 250 µA;
T
j
= 25 °C
V
GS
= 5 V; I
D
= 5 A;
T
j
= 25 °C; see
Figure 24;
see
Figure 26
T
j
= 25 °C; V
GS
= 5 V; see
Figure 28
V
GS
= 0 V; I
D
= 250 µA;
T
j
= 25 °C
Min
-
Typ
8.6
Max
10
Unit
mΩ
Symbol Parameter
Static characteristics, FET1
R
DSon
drain-source
on-state resistance
ratio of drain current
to sense current
I
D
/I
sense
8100
55
9000
-
9900
-
A/A
V
V
(BR)DSS
drain-source
breakdown voltage
Static characteristics, FET2
R
DSon
drain-source
on-state resistance
ratio of drain current
to sense current
-
21.3
25
mΩ
I
D
/I
sense
5910
55
6570
-
7227
-
A/A
V
V
(BR)DSS
drain-source
breakdown voltage
NXP Semiconductors
BUK9MGP-55PTS
Dual TrenchPLUS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pinning information
Symbol
G1
IS1
D1
A1
C1
G2
IS2
D2
A2
C2
D2
KS2
S2
S2
D2
D1
KS1
S1
S1
D1
Description
gate 1
current sense 1
drain 1
anode 1
cathode 1
gate 2
current sense 2
drain 2
anode 2
cathode 2
drain 2
Kelvin source 2
source 2
source 2
drain 2
drain 1
Kelvin source 1
source 1
source 1
drain 1
1
10
20
11
D1
A1
D2
A2
Simplified outline
Graphic symbol
FET1
FET2
SOT163-1
(SO20)
G1
IS1 S1 KS1 C1 G2
IS2 S2 KS2 C2
003aaa745
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9MGP-55PTS
SO20
Description
plastic small outline package; 20 leads; body width 7.5 mm
Version
SOT163-1
Type number
BUK9MGP-55PTS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 14 May 2009
2 of 20
NXP Semiconductors
BUK9MGP-55PTS
Dual TrenchPLUS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
T
sp
= 25 °C; V
GS
= 5 V; see
Figure 3;
see
Figure 7; [1][2]
T
sp
= 100 °C; V
GS
= 5 V; see
Figure 3;
T
sp
= 25 °C; t
p
≤
10 µs; pulsed; see
Figure 7
T
sp
= 25 °C; see
Figure 1
[1][2]
Conditions
25 °C < T
j
< 150 °C
R
GS
= 20 kΩ; 25 °C < T
j
< 150 °C
Min
-
-
-15
-
-
-
-
-55
-55
-
Max
55
55
15
16.9
10.7
349
5.2
150
150
100
Unit
V
V
V
A
A
A
W
°C
°C
V
In accordance with the Absolute Maximum Rating System (IEC 60134).
Limiting values, FET1
V
isol(FET-TSD)
FET to temperature
sense diode isolation
voltage
Limiting values, FET2
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
T
sp
= 25 °C; V
GS
= 5 V; see
Figure 4;
see
Figure 8; [1][2]
T
sp
= 100 °C; V
GS
= 5 V; see
Figure 4;
T
sp
= 25 °C; t
p
≤
10 µs; pulsed; see
Figure 8
T
sp
= 25 °C; see
Figure 2
[1][2]
25 °C < T
j
< 150 °C
R
GS
= 20 kΩ; 25 °C < T
j
< 150 °C
-
-
-15
-
-
-
-
-55
-55
-
55
55
15
9.16
5.8
148
3.9
150
150
100
V
V
V
A
A
A
W
°C
°C
V
V
isol(FET-TSD)
FET to temperature
sense diode isolation
voltage
Source-drain diode, FET1
I
S
I
SM
I
S
I
SM
E
DS(AL)S
source current
peak source current
source current
peak source current
T
sp
= 25 °C;
t
p
≤
10 µs; pulsed; T
sp
= 25 °C
T
sp
= 25 °C;
t
p
≤
10 µs; pulsed; T
sp
= 25 °C
[3][4]
[5]
[1][2]
[1][2]
-
-
-
-
-
7.3
349
5.5
148
929
A
A
A
A
mJ
Source-drain diode, FET2
Avalanche ruggedness, FET1
non-repetitive
I
D
= 16.9 A; V
sup
≤
55 V; V
GS
= 5 V; T
j(init)
= 25 °C;
drain-source avalanche unclamped; see
Figure 5;
energy
non-repetitive
I
D
= 9.16 A; V
sup
≤
55 V; V
GS
= 5 V; T
j(init)
= 25 °C;
drain-source avalanche unclamped; see
Figure 6;
energy
Avalanche ruggedness, FET2
E
DS(AL)S
[3][4]
[5]
-
360
mJ
BUK9MGP-55PTS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 14 May 2009
3 of 20
NXP Semiconductors
BUK9MGP-55PTS
Dual TrenchPLUS logic level FET
Table 4.
Symbol
V
ESD
Limiting values
…continued
Parameter
electrostatic discharge
voltage
Conditions
HBM; C = 100 pF; R = 1.5 kΩ; pins 3, 16 and 20 to
pins 1, 2, 17, 18 and 19 shorted
HBM; C = 100 pF; R = 1.5 kΩ; all pins
Min
-
-
-
-
Max
4
0.15
4
0.15
Unit
kV
kV
kV
kV
In accordance with the Absolute Maximum Rating System (IEC 60134).
Electrostatic discharge, FET1
Electrostatic discharge, FET2
V
ESD
electrostatic discharge
voltage
HBM; C = 100 pF; R = 1.5 kΩ; pins 8, 11 and 15 to
pins 6, 7, 12, 13 and 14 shorted
HBM; C = 100 pF; R = 1.5 kΩ; all pins
[1]
[2]
[3]
[4]
[5]
Single device conducting.
Current is limited by chip power dissipation rating.
Single-pulse avalanche rating limited by maximum junction temperature of 150 °C.
Repetitive rating defined in avalanche rating figure.
Refer to application note AN10273 for further information.
120
P
der
(%)
80
003aab388
120
P
der
(%)
80
003aab388
40
40
0
0
50
100
150
T
sp
200
(°C)
0
0
50
100
150
200
T
sp
(°C)
Fig 1.
Normalized total power dissipation as a
function of solder point temperature, FET1
Fig 2.
Normalized total power dissipation as a
function of solder point temperature, FET2
BUK9MGP-55PTS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 14 May 2009
4 of 20
NXP Semiconductors
BUK9MGP-55PTS
Dual TrenchPLUS logic level FET
20
I
D
(A)
16
003aac532
12
I
D
(A)
003aac533
8
12
8
4
4
0
0
50
100
150
T
sp
(°C)
200
0
0
50
100
150
T
sp
(°C)
200
Fig 3.
Continuous drain current as a function of
solder point temperature, FET1.
003aac527
Fig 4.
Continuous drain current as a function of
solder point temperature, FET2.
003aac528
10
2
I
AL
(A)
10
2
I
AL
(A)
10
(1)
10
(1)
(2)
(2)
1
1
(3)
(3)
10
-1
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
10
-1
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig 5.
Single-pulse and repetitive avalanche rating;
avalanche current as a function of avalanche
time, FET1
Fig 6.
Single-pulse and repetitive avalanche rating;
avalanche current as a function of avalanche
time, FET2
BUK9MGP-55PTS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 14 May 2009
5 of 20
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