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74LX1G14

产品描述TTL/H/L SERIES, 1-INPUT INVERT GATE, PDSO5
产品类别半导体    逻辑   
文件大小117KB,共11页
制造商ST(意法半导体)
官网地址http://www.st.com/
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74LX1G14概述

TTL/H/L SERIES, 1-INPUT INVERT GATE, PDSO5

74LX1G14规格参数

参数名称属性值
功能数量1
端子数量5
最大工作温度125 Cel
最小工作温度-55 Cel
最大供电/工作电压5.5 V
最小供电/工作电压1.65 V
额定供电电压1.8 V
加工封装描述SOT-323, 5 PIN
无铅Yes
欧盟RoHS规范Yes
状态ACTIVE
工艺CMOS
包装形状RECTANGULAR
包装尺寸SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
表面贴装Yes
端子形式GULL WING
端子间距0.6500 mm
端子涂层MATTE TIN
端子位置DUAL
包装材料PLASTIC/EPOXY
温度等级MILITARY
系列TTL/H/L
逻辑IC类型INVERT
输入数1
传播延迟TPD15.6 ns

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74LX1G14
LOW VOLTAGE CMOS SINGLE SCHMITT INVERTER
WITH 5V TOLERANT INPUT
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS
HIGH SPEED: t
PD
= 7.5ns (MAX.) at V
CC
= 3V
LOW POWER DISSIPATION:
I
CC
= 1µA (MAX.) at T
A
= 25°C
TYPICAL HYSTERESIS: V
h
=1V at V
CC
=4.5V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 5.5V
(1.2V Data Retention)
IMPROVED LATCH-UP IMMUNITY
SOT23-5L
SOT323-5L
ORDER CODES
PACKAGE
SOT23-5L
SOT323-5L
T&R
74LX1G14STR
74LX1G14CTR
DESCRIPTION
The 74LX1G14 is a low voltage CMOS SINGLE
SCHMITT INVERTER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
It is ideal for 1.65 to 5.5 V
CC
operations and low
power and low noise applications. The internal
circuit is composed of 3 stages including buffer
output, which provide high noise immunity and
stable output.
Power down protection is provided on input and
output and 0 to 7V can be accepted on inputs with
PIN CONNECTION AND IEC LOGIC SYMBOLS
no regard to the supply voltage. It can be
interfaced to 5V signal environment for inputs in
mixed 3.3/5V system.
Pin configuration and function are the same as
those of the 74LX1G04 but the 74LX1G14 has
hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
The input is equipped with protection circuits
against static discharge, giving it ESD immunity
and transient excess voltage.
April 2004
1/11

 
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